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radeonsi/gfx9: workaround for INTERP with indirect indexing 

and clean up the conditions.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Marek Olšák 2018-04-13 17:15:06 -04:00
parent 2d69b485f5
commit 6d19120da8
1 changed files with 13 additions and 6 deletions
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19
src/gallium/drivers/radeonsi/si_get.c
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@ -477,12 +477,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
/* TODO: Indirect indexing of GS inputs is unimplemented. */
return shader != PIPE_SHADER_GEOMETRY &&
(sscreen->llvm_has_working_vgpr_indexing ||
/* TCS and TES load inputs directly from LDS or
* offchip memory, so indirect indexing is trivial. */
shader == PIPE_SHADER_TESS_CTRL ||
shader == PIPE_SHADER_TESS_EVAL);
if (shader == PIPE_SHADER_GEOMETRY)
return 0;
if (shader == PIPE_SHADER_VERTEX &&
!sscreen->llvm_has_working_vgpr_indexing)
return 0;
/* TCS and TES load inputs directly from LDS or offchip
* memory, so indirect indexing is always supported.
* PS has to support indirect indexing, because we can't
* lower that to TEMPs for INTERP instructions.
*/
return 1;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return sscreen->llvm_has_working_vgpr_indexing ||