From 6cfc2e91e8381cddf0259c8b82e59a16eeb48c19 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sat, 28 May 2022 18:14:27 +0200 Subject: [PATCH] radv: Add performance counter reg write. Needed for reliably writing performance counter selectors. Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/common/sid.h | 1 + src/amd/vulkan/radv_cs.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index e94cb0ca707..9b30bc1da34 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -265,6 +265,7 @@ #define PKT3_IT_OPCODE_C 0xFFFF00FF #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) #define PKT3_SHADER_TYPE_S(x) (((unsigned)(x)&0x1) << 1) +#define PKT3_RESET_FILTER_CAM(x) (((unsigned)(x)&0x1) << 2) #define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) | PKT_COUNT_S(count)) #define PKT3(op, count, predicate) \ (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 7ecb13cbdae..782b686412a 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -184,6 +184,26 @@ radeon_set_uconfig_reg_idx(const struct radv_physical_device *pdevice, struct ra radeon_emit(cs, value); } +static inline void +radeon_set_perfctr_reg(struct radv_cmd_buffer *cmd_buffer, unsigned reg, unsigned value) +{ + struct radeon_cmdbuf *cs = cmd_buffer->cs; + assert(reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END); + assert(cs->cdw + 3 <= cs->max_dw); + + /* + * On GFX10, there is a bug with the ME implementation of its content addressable memory (CAM), + * that means that it can skip register writes due to not taking correctly into account the + * fields from the GRBM_GFX_INDEX. With this bit we can force the write. + */ + bool filter_cam_workaround = cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10 && + cmd_buffer->qf == RADV_QUEUE_GENERAL; + + radeon_emit(cs, PKT3(PKT3_SET_UCONFIG_REG, 1, 0) | PKT3_RESET_FILTER_CAM(filter_cam_workaround)); + radeon_emit(cs, (reg - CIK_UCONFIG_REG_OFFSET) >> 2); + radeon_emit(cs, value); +} + static inline void radeon_set_privileged_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) {