radv: enable DCC for layers on GFX8
It's currently only enabled if dcc_slice_size is equal to dcc_slice_fast_clear_size because the driver assumes that portions of multiple layers are contiguous but it's not always true. Still not supported on GFX9. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -171,14 +171,10 @@ radv_use_dcc_for_image(struct radv_device *device,
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return false;
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return false;
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/* TODO: Enable DCC for mipmaps on GFX9+. */
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/* TODO: Enable DCC for mipmaps on GFX9+. */
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if (pCreateInfo->mipLevels > 1 &&
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if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
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device->physical_device->rad_info.chip_class >= GFX9)
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device->physical_device->rad_info.chip_class >= GFX9)
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return false;
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return false;
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/* TODO: Enable DCC for array layers. */
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if (pCreateInfo->arrayLayers > 1)
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return false;
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/* Do not enable DCC for mipmapped arrays because performance is worse. */
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/* Do not enable DCC for mipmapped arrays because performance is worse. */
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if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
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if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
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return false;
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return false;
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@ -1018,10 +1014,28 @@ radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
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}
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}
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static inline bool
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static inline bool
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radv_image_can_enable_dcc(struct radv_image *image)
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radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
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{
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{
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return radv_image_can_enable_dcc_or_cmask(image) &&
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if (!radv_image_can_enable_dcc_or_cmask(image) ||
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radv_image_has_dcc(image);
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!radv_image_has_dcc(image))
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return false;
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/* On GFX8, DCC layers can be interleaved and it's currently only
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* enabled if slice size is equal to the per slice fast clear size
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* because the driver assumes that portions of multiple layers are
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* contiguous during fast clears.
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*/
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if (image->info.array_size > 1) {
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const struct legacy_surf_level *surf_level =
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&image->planes[0].surface.u.legacy.level[0];
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assert(device->physical_device->rad_info.chip_class == GFX8);
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if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
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return false;
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}
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return true;
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}
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}
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static inline bool
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static inline bool
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@ -1151,7 +1165,7 @@ radv_image_create(VkDevice _device,
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if (!create_info->no_metadata_planes) {
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if (!create_info->no_metadata_planes) {
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/* Try to enable DCC first. */
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/* Try to enable DCC first. */
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if (radv_image_can_enable_dcc(image)) {
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if (radv_image_can_enable_dcc(device, image)) {
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radv_image_alloc_dcc(image);
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radv_image_alloc_dcc(image);
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if (image->info.samples > 1) {
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if (image->info.samples > 1) {
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/* CMASK should be enabled because DCC fast
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/* CMASK should be enabled because DCC fast
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