iris: Remove remaining history flushes.
This removes a couple of remaining history flushes which were open-coded instead of using the iris_flush_and_dirty_for_history() helper. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15738>
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@ -2355,30 +2355,10 @@ iris_transfer_flush_region(struct pipe_context *ctx,
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if (map->staging)
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if (map->staging)
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iris_flush_staging_region(xfer, box);
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iris_flush_staging_region(xfer, box);
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uint32_t history_flush = 0;
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if (res->base.b.target == PIPE_BUFFER) {
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if (res->base.b.target == PIPE_BUFFER) {
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if (map->staging)
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history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH |
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PIPE_CONTROL_TILE_CACHE_FLUSH;
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if (map->dest_had_defined_contents)
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history_flush |= iris_flush_bits_for_history(ice, res);
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util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
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util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
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}
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}
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if (history_flush & ~PIPE_CONTROL_CS_STALL) {
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iris_foreach_batch(ice, batch) {
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if (batch->contains_draw || batch->cache.render->entries) {
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iris_batch_maybe_flush(batch, 24);
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iris_emit_pipe_control_flush(batch,
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"cache history: transfer flush",
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history_flush);
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}
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}
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}
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/* Make sure we flag constants dirty even if there's no need to emit
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/* Make sure we flag constants dirty even if there's no need to emit
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* any PIPE_CONTROLs to a batch.
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* any PIPE_CONTROLs to a batch.
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*/
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*/
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@ -2536,37 +2516,6 @@ iris_dirty_for_history(struct iris_context *ice,
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ice->state.stage_dirty |= stage_dirty;
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ice->state.stage_dirty |= stage_dirty;
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}
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}
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/**
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* Produce a set of PIPE_CONTROL bits which ensure data written to a
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* resource becomes visible, and any stale read cache data is invalidated.
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*/
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uint32_t
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iris_flush_bits_for_history(struct iris_context *ice,
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struct iris_resource *res)
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{
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struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen;
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uint32_t flush = PIPE_CONTROL_CS_STALL;
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if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
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flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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flush |= screen->compiler->indirect_ubos_use_sampler ?
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE :
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PIPE_CONTROL_DATA_CACHE_FLUSH;
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}
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if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
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flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
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if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
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flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
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if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
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flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
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return flush;
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}
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bool
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bool
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iris_resource_set_clear_color(struct iris_context *ice,
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iris_resource_set_clear_color(struct iris_context *ice,
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struct iris_resource *res,
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struct iris_resource *res,
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@ -339,9 +339,6 @@ void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
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void iris_dirty_for_history(struct iris_context *ice,
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void iris_dirty_for_history(struct iris_context *ice,
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struct iris_resource *res);
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struct iris_resource *res);
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uint32_t iris_flush_bits_for_history(struct iris_context *ice,
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struct iris_resource *res);
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unsigned iris_get_num_logical_layers(const struct iris_resource *res,
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unsigned iris_get_num_logical_layers(const struct iris_resource *res,
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unsigned level);
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unsigned level);
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@ -3855,27 +3855,14 @@ iris_set_stream_output_targets(struct pipe_context *ctx,
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if (active) {
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if (active) {
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ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST;
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ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST;
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} else {
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} else {
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uint32_t flush = 0;
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for (int i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
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for (int i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
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struct iris_stream_output_target *tgt =
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struct iris_stream_output_target *tgt =
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(void *) ice->state.so_target[i];
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(void *) ice->state.so_target[i];
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if (tgt) {
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struct iris_resource *res = (void *) tgt->base.buffer;
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flush |= iris_flush_bits_for_history(ice, res);
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if (tgt)
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iris_dirty_for_history(ice, res);
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iris_dirty_for_history(ice, (void *)tgt->base.buffer);
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}
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}
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}
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}
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#if GFX_VER >= 12
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/* SO draws require flushing of const cache to make SO data
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* observable when VB/IB are cached in L3.
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*/
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if (flush & PIPE_CONTROL_VF_CACHE_INVALIDATE)
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flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
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#endif
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iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_RENDER],
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"make streamout results visible", flush);
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}
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}
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}
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for (int i = 0; i < 4; i++) {
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for (int i = 0; i < 4; i++) {
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