KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

iris: Remove remaining history flushes. 

This removes a couple of remaining history flushes which were
open-coded instead of using the iris_flush_and_dirty_for_history()
helper.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15738>
This commit is contained in:
Francisco Jerez 2020-02-05 18:26:39 -08:00 committed by Kenneth Graunke
parent bbb103be0e
commit 6cc09699cd
3 changed files with 2 additions and 69 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

51
src/gallium/drivers/iris/iris_resource.c
View File

@ -2355,30 +2355,10 @@ iris_transfer_flush_region(struct pipe_context *ctx,
if (map->staging)
iris_flush_staging_region(xfer, box);
uint32_t history_flush = 0;
if (res->base.b.target == PIPE_BUFFER) {
if (map->staging)
history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_TILE_CACHE_FLUSH;
if (map->dest_had_defined_contents)
history_flush |= iris_flush_bits_for_history(ice, res);
util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
}
if (history_flush & ~PIPE_CONTROL_CS_STALL) {
iris_foreach_batch(ice, batch) {
if (batch->contains_draw || batch->cache.render->entries) {
iris_batch_maybe_flush(batch, 24);
iris_emit_pipe_control_flush(batch,
"cache history: transfer flush",
history_flush);
}
}
}
/* Make sure we flag constants dirty even if there's no need to emit
* any PIPE_CONTROLs to a batch.
*/
@ -2536,37 +2516,6 @@ iris_dirty_for_history(struct iris_context *ice,
ice->state.stage_dirty |= stage_dirty;
}
/**
* Produce a set of PIPE_CONTROL bits which ensure data written to a
* resource becomes visible, and any stale read cache data is invalidated.
*/
uint32_t
iris_flush_bits_for_history(struct iris_context *ice,
struct iris_resource *res)
{
struct iris_screen *screen = (struct iris_screen *) ice->ctx.screen;
uint32_t flush = PIPE_CONTROL_CS_STALL;
if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
flush |= screen->compiler->indirect_ubos_use_sampler ?
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE :
PIPE_CONTROL_DATA_CACHE_FLUSH;
}
if (res->bind_history & PIPE_BIND_SAMPLER_VIEW)
flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE))
flush |= PIPE_CONTROL_DATA_CACHE_FLUSH;
return flush;
}
bool
iris_resource_set_clear_color(struct iris_context *ice,
struct iris_resource *res,

3
src/gallium/drivers/iris/iris_resource.h
View File

@ -339,9 +339,6 @@ void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
void iris_dirty_for_history(struct iris_context *ice,
struct iris_resource *res);
uint32_t iris_flush_bits_for_history(struct iris_context *ice,
struct iris_resource *res);
unsigned iris_get_num_logical_layers(const struct iris_resource *res,
unsigned level);

17
src/gallium/drivers/iris/iris_state.c
View File

@ -3855,26 +3855,13 @@ iris_set_stream_output_targets(struct pipe_context *ctx,
if (active) {
ice->state.dirty |= IRIS_DIRTY_SO_DECL_LIST;
} else {
uint32_t flush = 0;
for (int i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
struct iris_stream_output_target *tgt =
(void *) ice->state.so_target[i];
if (tgt) {
struct iris_resource *res = (void *) tgt->base.buffer;
flush |= iris_flush_bits_for_history(ice, res);
iris_dirty_for_history(ice, res);
}
if (tgt)
iris_dirty_for_history(ice, (void *)tgt->base.buffer);
}
#if GFX_VER >= 12
/* SO draws require flushing of const cache to make SO data
* observable when VB/IB are cached in L3.
*/
if (flush & PIPE_CONTROL_VF_CACHE_INVALIDATE)
flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
#endif
iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_RENDER],
"make streamout results visible", flush);
}
}