cell: Added TRUNC, SWZ (extended) and XPD instructions, verified against softpipe. Optimized FLR and FRC. Fixed writeback logic for DP3, DP4 and DPH.
This commit is contained in:
Jonathan White
parent
56c476395f
commit
6b3ec9ec2b
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@ -181,8 +181,8 @@ get_src_reg(struct codegen *gen,
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boolean reg_is_itemp = FALSE;
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uint sign_op;
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assert(swizzle >= 0);
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assert(swizzle <= 3);
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assert(swizzle >= TGSI_SWIZZLE_X);
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assert(swizzle <= TGSI_EXTSWIZZLE_ONE);
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channel = swizzle;
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@ -192,12 +192,28 @@ get_src_reg(struct codegen *gen,
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break;
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case TGSI_FILE_INPUT:
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{
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/* offset is measured in quadwords, not bytes */
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int offset = src->SrcRegister.Index * 4 + channel;
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reg = get_itemp(gen);
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reg_is_itemp = TRUE;
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/* Load: reg = memory[(machine_reg) + offset] */
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spe_lqd(gen->f, reg, gen->inputs_reg, offset);
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if(channel == TGSI_EXTSWIZZLE_ONE)
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{
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/* Load const one float and early out */
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reg = get_const_one_reg(gen);
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return reg;
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}
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else if(channel == TGSI_EXTSWIZZLE_ZERO)
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{
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/* Load const zero float and early out */
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reg = get_itemp(gen);
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spe_xor(gen->f, reg, reg, reg);
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return reg;
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}
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else
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{
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/* offset is measured in quadwords, not bytes */
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int offset = src->SrcRegister.Index * 4 + channel;
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reg = get_itemp(gen);
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reg_is_itemp = TRUE;
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/* Load: reg = memory[(machine_reg) + offset] */
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spe_lqd(gen->f, reg, gen->inputs_reg, offset);
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}
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}
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break;
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case TGSI_FILE_IMMEDIATE:
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@ -355,8 +371,6 @@ emit_MOV(struct codegen *gen, const struct tgsi_full_instruction *inst)
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return true;
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}
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/**
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* Emit addition instructions. Recall that a single TGSI_OPCODE_ADD
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* becomes (up to) four SPU "fa" instructions because we're doing SOA
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@ -569,23 +583,23 @@ emit_DP3(struct codegen *gen, const struct tgsi_full_instruction *inst)
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int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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int d_reg = get_dst_reg(gen, CHAN_X, &inst->FullDstRegisters[0]);
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/* d = x * x */
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spe_fm(gen->f, d_reg, s1_reg, s2_reg);
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int tmp_reg = get_itemp(gen);
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/* t = x0 * x1 */
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spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
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s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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/* d = y * y + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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/* t = y0 * y1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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/* d = z * z + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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/* t = z0 * z1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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store_dest_reg(gen, tmp_reg, ch, &inst->FullDstRegisters[0]);
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}
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}
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@ -600,32 +614,32 @@ static boolean
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emit_DP4(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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spe_comment(gen->f, -4, "DP3:");
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spe_comment(gen->f, -4, "DP4:");
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int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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int d_reg = get_dst_reg(gen, CHAN_X, &inst->FullDstRegisters[0]);
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/* d = x * x */
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spe_fm(gen->f, d_reg, s1_reg, s2_reg);
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int tmp_reg = get_itemp(gen);
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/* t = x0 * x1 */
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spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
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s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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/* d = y * y + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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/* t = y0 * y1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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/* d = z * z + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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/* t = z0 * z1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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s1_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
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/* d = w * w + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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/* t = w0 * w1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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store_dest_reg(gen, tmp_reg, ch, &inst->FullDstRegisters[0]);
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}
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}
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@ -644,27 +658,28 @@ emit_DPH(struct codegen *gen, const struct tgsi_full_instruction *inst)
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int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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int d_reg = get_dst_reg(gen, CHAN_X, &inst->FullDstRegisters[0]);
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/* d = x * x */
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spe_fm(gen->f, d_reg, s1_reg, s2_reg);
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int tmp_reg = get_itemp(gen);
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/* t = x0 * x1 */
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spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
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s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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/* d = y * y + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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/* t = y0 * y1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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/* d = z * z + d */
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spe_fma(gen->f, d_reg, s1_reg, s2_reg, d_reg);
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/* t = z0 * z1 + t */
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spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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s2_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
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/* d = w + d */
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spe_fa(gen->f, d_reg, s2_reg, d_reg);
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/* t = w1 + t */
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spe_fa(gen->f, tmp_reg, s2_reg, tmp_reg);
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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store_dest_reg(gen, tmp_reg, ch, &inst->FullDstRegisters[0]);
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}
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}
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@ -672,6 +687,62 @@ emit_DPH(struct codegen *gen, const struct tgsi_full_instruction *inst)
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return true;
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}
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/**
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* Emit cross product. See emit_ADD for comments.
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*/
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static boolean
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emit_XPD(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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spe_comment(gen->f, -4, "XPD:");
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int s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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int s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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int tmp_reg = get_itemp(gen);
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/* t = z0 * y1 */
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spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
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s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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/* t = y0 * z1 - t */
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spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_X)) {
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store_dest_reg(gen, tmp_reg, CHAN_X, &inst->FullDstRegisters[0]);
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}
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s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
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/* t = x0 * z1 */
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spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
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s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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/* t = z0 * x1 - t */
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spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_Y)) {
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store_dest_reg(gen, tmp_reg, CHAN_Y, &inst->FullDstRegisters[0]);
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}
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s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
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/* t = y0 * x1 */
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spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
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s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
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s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
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/* t = x0 * y1 - t */
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spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_Z)) {
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store_dest_reg(gen, tmp_reg, CHAN_Z, &inst->FullDstRegisters[0]);
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}
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free_itemps(gen);
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return true;
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}
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/**
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* Emit set-if-greater-than.
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* Note that the SPE fcgt instruction produces 0x0 and 0xffffffff as
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@ -894,6 +965,37 @@ emit_CMP(struct codegen *gen, const struct tgsi_full_instruction *inst)
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return true;
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}
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/**
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* Emit trunc.
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* Convert float to signed int
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* Convert signed int to float
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*/
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static boolean
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emit_TRUNC(struct codegen *gen, const struct tgsi_full_instruction *inst)
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{
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int ch;
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spe_comment(gen->f, -4, "TRUNC:");
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
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/* Convert float to int */
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spe_cflts(gen->f, d_reg, s1_reg, 0);
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/* Convert int to float */
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spe_csflt(gen->f, d_reg, d_reg, 0);
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store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
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free_itemps(gen);
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}
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}
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return true;
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}
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/**
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* Emit floor.
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* If negative int subtract one
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@ -907,6 +1009,9 @@ emit_FLR(struct codegen *gen, const struct tgsi_full_instruction *inst)
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spe_comment(gen->f, -4, "FLR:");
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int zero_reg = get_itemp(gen);
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spe_xor(gen->f, zero_reg, zero_reg, zero_reg);
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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@ -914,9 +1019,8 @@ emit_FLR(struct codegen *gen, const struct tgsi_full_instruction *inst)
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int tmp_reg = get_itemp(gen);
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/* If negative, subtract 1.0 */
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spe_xor(gen->f, tmp_reg, tmp_reg, tmp_reg);
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spe_fcgt(gen->f, d_reg, tmp_reg, s1_reg);
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spe_selb(gen->f, tmp_reg, tmp_reg, get_const_one_reg(gen), d_reg);
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spe_fcgt(gen->f, d_reg, zero_reg, s1_reg);
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spe_selb(gen->f, tmp_reg, zero_reg, get_const_one_reg(gen), d_reg);
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spe_fs(gen->f, d_reg, s1_reg, tmp_reg);
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/* Convert float to int */
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@ -944,6 +1048,9 @@ emit_FRC(struct codegen *gen, const struct tgsi_full_instruction *inst)
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spe_comment(gen->f, -4, "FLR:");
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int zero_reg = get_itemp(gen);
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spe_xor(gen->f, zero_reg, zero_reg, zero_reg);
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for (ch = 0; ch < 4; ch++) {
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if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch)) {
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int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
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@ -951,9 +1058,8 @@ emit_FRC(struct codegen *gen, const struct tgsi_full_instruction *inst)
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int tmp_reg = get_itemp(gen);
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/* If negative, subtract 1.0 */
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spe_xor(gen->f, tmp_reg, tmp_reg, tmp_reg);
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spe_fcgt(gen->f, d_reg, tmp_reg, s1_reg);
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spe_selb(gen->f, tmp_reg, tmp_reg, get_const_one_reg(gen), d_reg);
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spe_fcgt(gen->f, d_reg, zero_reg, s1_reg);
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spe_selb(gen->f, tmp_reg, zero_reg, get_const_one_reg(gen), d_reg);
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spe_fs(gen->f, d_reg, s1_reg, tmp_reg);
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/* Convert float to int */
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@ -1148,6 +1254,7 @@ emit_instruction(struct codegen *gen,
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{
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switch (inst->Instruction.Opcode) {
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case TGSI_OPCODE_MOV:
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case TGSI_OPCODE_SWZ:
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return emit_MOV(gen, inst);
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case TGSI_OPCODE_MUL:
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return emit_MUL(gen, inst);
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@ -1165,6 +1272,8 @@ emit_instruction(struct codegen *gen,
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return emit_DP4(gen, inst);
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case TGSI_OPCODE_DPH:
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return emit_DPH(gen, inst);
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case TGSI_OPCODE_XPD:
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return emit_XPD(gen, inst);
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case TGSI_OPCODE_RCP:
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return emit_RCP(gen, inst);
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case TGSI_OPCODE_RSQ:
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@ -1189,6 +1298,8 @@ emit_instruction(struct codegen *gen,
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return emit_MAX(gen, inst);
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case TGSI_OPCODE_MIN:
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return emit_MIN(gen, inst);
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case TGSI_OPCODE_TRUNC:
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return emit_TRUNC(gen, inst);
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case TGSI_OPCODE_FLR:
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return emit_FLR(gen, inst);
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case TGSI_OPCODE_FRC:
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