intel/nir: Take a nir_tex_instr and src index in brw_texture_offset
This makes things a bit simpler and it's also more robust because it no longer has a hard dependency on the offset being a 32-bit value.
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@ -5062,14 +5062,8 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
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break;
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case nir_tex_src_offset: {
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nir_const_value *const_offset =
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nir_src_as_const_value(instr->src[i].src);
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assert(nir_src_bit_size(instr->src[i].src) == 32);
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unsigned offset_bits = 0;
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if (const_offset &&
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brw_texture_offset(const_offset->i32,
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nir_tex_instr_src_size(instr, i),
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&offset_bits)) {
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uint32_t offset_bits = 0;
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if (brw_texture_offset(instr, i, &offset_bits)) {
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header_bits |= offset_bits;
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} else {
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srcs[TEX_LOGICAL_SRC_TG4_OFFSET] =
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@ -129,26 +129,34 @@ brw_math_function(enum opcode op)
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}
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bool
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brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
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brw_texture_offset(const nir_tex_instr *tex, unsigned src,
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uint32_t *offset_bits_out)
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{
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if (!offsets) return false; /* nonconstant offset; caller will handle it. */
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/* offset out of bounds; caller will handle it. */
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for (unsigned i = 0; i < num_components; i++)
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if (offsets[i] > 7 || offsets[i] < -8)
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if (!nir_src_is_const(tex->src[src].src))
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return false;
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const unsigned num_components = nir_tex_instr_src_size(tex, src);
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/* Combine all three offsets into a single unsigned dword:
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*
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* bits 11:8 - U Offset (X component)
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* bits 7:4 - V Offset (Y component)
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* bits 3:0 - R Offset (Z component)
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*/
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*offset_bits = 0;
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uint32_t offset_bits = 0;
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for (unsigned i = 0; i < num_components; i++) {
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int offset = nir_src_comp_as_int(tex->src[src].src, i);
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/* offset out of bounds; caller will handle it. */
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if (offset > 7 || offset < -8)
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return false;
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const unsigned shift = 4 * (2 - i);
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*offset_bits |= (offsets[i] << shift) & (0xF << shift);
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offset_bits |= (offset << shift) & (0xF << shift);
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}
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*offset_bits_out = offset_bits;
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return true;
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}
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@ -243,8 +243,7 @@ public:
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virtual void invalidate_live_intervals() = 0;
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};
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bool brw_texture_offset(int *offsets,
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unsigned num_components,
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bool brw_texture_offset(const nir_tex_instr *tex, unsigned src,
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uint32_t *offset_bits);
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#else
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@ -2061,19 +2061,12 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
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break;
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}
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case nir_tex_src_offset: {
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nir_const_value *const_offset =
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nir_src_as_const_value(instr->src[i].src);
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assert(nir_src_bit_size(instr->src[i].src) == 32);
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if (!const_offset ||
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!brw_texture_offset(const_offset->i32,
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nir_tex_instr_src_size(instr, i),
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&constant_offset)) {
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case nir_tex_src_offset:
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if (!brw_texture_offset(instr, i, &constant_offset)) {
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offset_value =
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get_nir_src(instr->src[i].src, BRW_REGISTER_TYPE_D, 2);
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}
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break;
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}
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case nir_tex_src_texture_offset: {
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/* Emit code to evaluate the actual indexing expression */
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