pan/mdg: Implement b2f16
...as iand Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
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@ -581,7 +581,7 @@ nir_accepts_inot(nir_op op, unsigned src)
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{
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switch (op) {
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case nir_op_ior:
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case nir_op_iand:
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case nir_op_iand: /* TODO: b2f16 */
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case nir_op_ixor:
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return true;
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case nir_op_b32csel:
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@ -766,6 +766,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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*/
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ALU_CASE_CMP(b2f32, iand, true);
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ALU_CASE_CMP(b2f16, iand, true);
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ALU_CASE_CMP(b2i32, iand, true);
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/* Likewise, we don't have a dedicated f2b32 instruction, but
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@ -1016,13 +1017,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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ins.alu = alu;
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/* Arrange for creation of iandnot/iornot */
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if (ins.src_invert[0] && !ins.src_invert[1]) {
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mir_flip(&ins);
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ins.src_invert[0] = false;
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ins.src_invert[1] = true;
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}
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/* Late fixup for emulated instructions */
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if (instr->op == nir_op_b2f32 || instr->op == nir_op_b2i32) {
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@ -1041,6 +1035,14 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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else
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ins.constants.i32[0] = 1;
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for (unsigned c = 0; c < 16; ++c)
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ins.swizzle[1][c] = 0;
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} else if (instr->op == nir_op_b2f16) {
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ins.src[1] = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
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ins.src_types[1] = nir_type_float16;
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ins.has_constants = true;
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ins.constants.i16[0] = _mesa_float_to_half(1.0);
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for (unsigned c = 0; c < 16; ++c)
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ins.swizzle[1][c] = 0;
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} else if (nr_inputs == 1 && !quirk_flipped_r24) {
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@ -1055,6 +1057,13 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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ins.swizzle[1][c] = 0;
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}
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/* Arrange for creation of iandnot/iornot */
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if (ins.src_invert[0] && !ins.src_invert[1]) {
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mir_flip(&ins);
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ins.src_invert[0] = false;
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ins.src_invert[1] = true;
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}
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if ((opcode_props & UNITS_ALL) == UNIT_VLUT) {
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/* To avoid duplicating the lookup tables (probably), true LUT
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* instructions can only operate as if they were scalars. Lower
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