panfrost: Simplify depth/stencil/alpha
The alpha test is lowered by the frontend so we can drop that unused code path, and stencil state can be computed at CSO create time to reduce draw-time complexity. Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6195>
This commit is contained in:
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1675d92d66
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6afd4addef
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@ -160,11 +160,7 @@ panfrost_shader_compile(struct panfrost_context *ctx,
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s->info.stage = stage;
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/* Call out to Midgard compiler given the above NIR */
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panfrost_program program = {
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.alpha_ref = state->alpha_state.ref_value
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};
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panfrost_program program = {};
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memcpy(program.rt_formats, state->rt_formats, sizeof(program.rt_formats));
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if (dev->quirks & IS_BIFROST) {
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@ -349,72 +349,6 @@ panfrost_shader_meta_init(struct panfrost_context *ctx,
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}
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}
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static unsigned
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panfrost_translate_compare_func(enum pipe_compare_func in)
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{
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switch (in) {
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case PIPE_FUNC_NEVER:
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return MALI_FUNC_NEVER;
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case PIPE_FUNC_LESS:
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return MALI_FUNC_LESS;
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case PIPE_FUNC_EQUAL:
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return MALI_FUNC_EQUAL;
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case PIPE_FUNC_LEQUAL:
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return MALI_FUNC_LEQUAL;
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case PIPE_FUNC_GREATER:
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return MALI_FUNC_GREATER;
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case PIPE_FUNC_NOTEQUAL:
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return MALI_FUNC_NOT_EQUAL;
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case PIPE_FUNC_GEQUAL:
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return MALI_FUNC_GEQUAL;
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case PIPE_FUNC_ALWAYS:
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return MALI_FUNC_ALWAYS;
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default:
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unreachable("Invalid func");
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}
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}
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static unsigned
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panfrost_translate_stencil_op(enum pipe_stencil_op in)
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{
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switch (in) {
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case PIPE_STENCIL_OP_KEEP:
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return MALI_STENCIL_OP_KEEP;
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case PIPE_STENCIL_OP_ZERO:
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return MALI_STENCIL_OP_ZERO;
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case PIPE_STENCIL_OP_REPLACE:
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return MALI_STENCIL_OP_REPLACE;
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case PIPE_STENCIL_OP_INCR:
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return MALI_STENCIL_OP_INCR_SAT;
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case PIPE_STENCIL_OP_DECR:
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return MALI_STENCIL_OP_DECR_SAT;
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case PIPE_STENCIL_OP_INCR_WRAP:
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return MALI_STENCIL_OP_INCR_WRAP;
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case PIPE_STENCIL_OP_DECR_WRAP:
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return MALI_STENCIL_OP_DECR_WRAP;
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case PIPE_STENCIL_OP_INVERT:
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return MALI_STENCIL_OP_INVERT;
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default:
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unreachable("Invalid stencil op");
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}
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}
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static unsigned
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translate_tex_wrap(enum pipe_tex_wrap w)
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{
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@ -517,19 +451,6 @@ void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso,
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hw->max_lod = hw->min_lod + 1;
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}
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static void
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panfrost_make_stencil_state(const struct pipe_stencil_state *in,
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void *out)
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{
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pan_pack(out, STENCIL, cfg) {
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cfg.mask = in->valuemask;
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cfg.compare_function = panfrost_translate_compare_func(in->func);
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cfg.stencil_fail = panfrost_translate_stencil_op(in->fail_op);
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cfg.depth_fail = panfrost_translate_stencil_op(in->zfail_op);
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cfg.depth_pass = panfrost_translate_stencil_op(in->zpass_op);
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}
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}
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static void
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panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx,
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struct mali_shader_meta *fragmeta)
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@ -578,43 +499,37 @@ static void
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panfrost_frag_meta_zsa_update(struct panfrost_context *ctx,
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struct mali_shader_meta *fragmeta)
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{
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const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
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const struct panfrost_zsa_state *so = ctx->depth_stencil;
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int zfunc = PIPE_FUNC_ALWAYS;
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if (!zsa) {
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if (!so) {
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/* If stenciling is disabled, the state is irrelevant */
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SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false);
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SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false);
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} else {
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SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST,
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zsa->stencil[0].enabled);
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panfrost_make_stencil_state(&zsa->stencil[0],
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&fragmeta->stencil_front);
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fragmeta->stencil_mask_front = zsa->stencil[0].writemask;
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so->base.stencil[0].enabled);
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/* Bottom 8-bits of stencil state is the stencil ref, ref is no
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* more than 8-bits. Be extra careful. */
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fragmeta->stencil_front.opaque[0] |= ctx->stencil_ref.ref_value[0];
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fragmeta->stencil_mask_front = so->stencil_mask_front;
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fragmeta->stencil_mask_back = so->stencil_mask_back;
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/* Bottom bits for stencil ref, exactly one word */
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fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0];
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/* If back-stencil is not enabled, use the front values */
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if (zsa->stencil[1].enabled) {
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panfrost_make_stencil_state(&zsa->stencil[1],
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&fragmeta->stencil_back);
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fragmeta->stencil_mask_back = zsa->stencil[1].writemask;
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fragmeta->stencil_back.opaque[0] |= ctx->stencil_ref.ref_value[1];
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} else {
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if (so->base.stencil[1].enabled)
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fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1];
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else
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fragmeta->stencil_back = fragmeta->stencil_front;
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fragmeta->stencil_mask_back = fragmeta->stencil_mask_front;
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}
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if (zsa->depth.enabled)
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zfunc = zsa->depth.func;
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if (so->base.depth.enabled)
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zfunc = so->base.depth.func;
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/* Depth state (TODO: Refactor) */
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SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK,
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zsa->depth.writemask);
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so->base.depth.writemask);
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}
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fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK;
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@ -864,7 +779,7 @@ panfrost_frag_shader_meta_init(struct panfrost_context *ctx,
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* depends on if depth/stencil is used for the draw or not.
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* Just one of depth OR stencil is enough to trigger this. */
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const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil;
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const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base;
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bool zs_enabled = fs->writes_depth || fs->writes_stencil;
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if (zsa) {
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@ -114,4 +114,20 @@ panfrost_vt_update_primitive_size(struct panfrost_context *ctx,
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mali_ptr
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panfrost_emit_sample_locations(struct panfrost_batch *batch);
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static inline unsigned
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panfrost_translate_compare_func(enum pipe_compare_func in)
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{
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switch (in) {
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case PIPE_FUNC_NEVER: return MALI_FUNC_NEVER;
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case PIPE_FUNC_LESS: return MALI_FUNC_LESS;
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case PIPE_FUNC_EQUAL: return MALI_FUNC_EQUAL;
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case PIPE_FUNC_LEQUAL: return MALI_FUNC_LEQUAL;
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case PIPE_FUNC_GREATER: return MALI_FUNC_GREATER;
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case PIPE_FUNC_NOTEQUAL: return MALI_FUNC_NOT_EQUAL;
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case PIPE_FUNC_GEQUAL: return MALI_FUNC_GEQUAL;
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case PIPE_FUNC_ALWAYS: return MALI_FUNC_ALWAYS;
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default: unreachable("Invalid func");
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}
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}
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#endif /* __PAN_CMDSTREAM_H__ */
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@ -636,25 +636,9 @@ panfrost_variant_matches(
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{
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struct panfrost_device *dev = pan_device(ctx->base.screen);
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struct pipe_rasterizer_state *rasterizer = &ctx->rasterizer->base;
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struct pipe_alpha_state *alpha = &ctx->depth_stencil->alpha;
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bool is_fragment = (type == PIPE_SHADER_FRAGMENT);
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if (is_fragment && (alpha->enabled || variant->alpha_state.enabled)) {
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/* Make sure enable state is at least the same */
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if (alpha->enabled != variant->alpha_state.enabled) {
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return false;
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}
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/* Check that the contents of the test are the same */
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bool same_func = alpha->func == variant->alpha_state.func;
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bool same_ref = alpha->ref_value == variant->alpha_state.ref_value;
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if (!(same_func && same_ref)) {
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return false;
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}
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}
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if (variant->outputs_read) {
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struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
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&variants->variants[variant];
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if (type == PIPE_SHADER_FRAGMENT) {
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v->alpha_state = ctx->depth_stencil->alpha;
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struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer;
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for (unsigned i = 0; i < fb->nr_cbufs; ++i) {
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enum pipe_format fmt = PIPE_FORMAT_R8G8B8A8_UNORM;
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ctx->base.bind_fs_state(&ctx->base, fs);
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}
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static inline unsigned
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pan_pipe_to_stencil_op(enum pipe_stencil_op in)
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{
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switch (in) {
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case PIPE_STENCIL_OP_KEEP: return MALI_STENCIL_OP_KEEP;
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case PIPE_STENCIL_OP_ZERO: return MALI_STENCIL_OP_ZERO;
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case PIPE_STENCIL_OP_REPLACE: return MALI_STENCIL_OP_REPLACE;
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case PIPE_STENCIL_OP_INCR: return MALI_STENCIL_OP_INCR_SAT;
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case PIPE_STENCIL_OP_DECR: return MALI_STENCIL_OP_DECR_SAT;
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case PIPE_STENCIL_OP_INCR_WRAP: return MALI_STENCIL_OP_INCR_WRAP;
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case PIPE_STENCIL_OP_DECR_WRAP: return MALI_STENCIL_OP_DECR_WRAP;
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case PIPE_STENCIL_OP_INVERT: return MALI_STENCIL_OP_INVERT;
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default: unreachable("Invalid stencil op");
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}
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}
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static inline void
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pan_pipe_to_stencil(const struct pipe_stencil_state *in, void *out)
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{
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pan_pack(out, STENCIL, cfg) {
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cfg.mask = in->valuemask;
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cfg.compare_function = panfrost_translate_compare_func(in->func);
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cfg.stencil_fail = pan_pipe_to_stencil_op(in->fail_op);
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cfg.depth_fail = pan_pipe_to_stencil_op(in->zfail_op);
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cfg.depth_pass = pan_pipe_to_stencil_op(in->zpass_op);
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}
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}
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static void *
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panfrost_create_depth_stencil_state(struct pipe_context *pipe,
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const struct pipe_depth_stencil_alpha_state *depth_stencil)
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const struct pipe_depth_stencil_alpha_state *zsa)
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{
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return mem_dup(depth_stencil, sizeof(*depth_stencil));
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struct panfrost_zsa_state *so = CALLOC_STRUCT(panfrost_zsa_state);
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so->base = *zsa;
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pan_pipe_to_stencil(&zsa->stencil[0], &so->stencil_front);
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pan_pipe_to_stencil(&zsa->stencil[1], &so->stencil_back);
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so->stencil_mask_front = zsa->stencil[0].writemask;
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if (zsa->stencil[1].enabled)
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so->stencil_mask_back = zsa->stencil[1].writemask;
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else
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so->stencil_mask_back = so->stencil_mask_front;
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/* Alpha lowered by frontend */
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assert(!zsa->alpha.enabled);
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/* TODO: Bounds test should be easy */
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assert(!zsa->depth.bounds_test);
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return so;
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}
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static void
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@ -1145,22 +1174,8 @@ panfrost_bind_depth_stencil_state(struct pipe_context *pipe,
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void *cso)
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{
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struct panfrost_context *ctx = pan_context(pipe);
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struct pipe_depth_stencil_alpha_state *depth_stencil = cso;
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ctx->depth_stencil = depth_stencil;
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if (!depth_stencil)
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return;
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/* Alpha does not exist in the hardware (it's not in ES3), so it's
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* emulated in the fragment shader */
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if (depth_stencil->alpha.enabled) {
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/* We need to trigger a new shader (maybe) */
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ctx->base.bind_fs_state(&ctx->base, ctx->shader[PIPE_SHADER_FRAGMENT]);
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}
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/* Bounds test not implemented */
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assert(!depth_stencil->depth.bounds_test);
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struct panfrost_zsa_state *zsa = cso;
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ctx->depth_stencil = zsa;
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}
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static void
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@ -162,7 +162,7 @@ struct panfrost_context {
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struct pipe_viewport_state pipe_viewport;
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struct pipe_scissor_state scissor;
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struct pipe_blend_color blend_color;
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struct pipe_depth_stencil_alpha_state *depth_stencil;
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struct panfrost_zsa_state *depth_stencil;
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struct pipe_stencil_ref stencil_ref;
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unsigned sample_mask;
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unsigned min_samples;
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@ -177,8 +177,7 @@ struct panfrost_rasterizer {
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};
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/* Variants bundle together to form the backing CSO, bundling multiple
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* shaders with varying emulated features baked in (alpha test
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* parameters, etc) */
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* shaders with varying emulated features baked in */
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/* A shader state corresponds to the actual, current variant of the shader */
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struct panfrost_shader_state {
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@ -217,9 +216,6 @@ struct panfrost_shader_state {
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unsigned sysval_count;
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unsigned sysval[MAX_SYSVAL_COUNT];
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/* Information on this particular shader variant */
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struct pipe_alpha_state alpha_state;
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uint16_t point_sprite_mask;
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unsigned point_sprite_upper_left : 1;
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@ -261,6 +257,16 @@ struct panfrost_vertex_state {
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struct mali_attr_meta hw[PIPE_MAX_ATTRIBS];
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};
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struct panfrost_zsa_state {
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struct pipe_depth_stencil_alpha_state base;
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/* Precomputed stencil state */
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struct mali_stencil_packed stencil_front;
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struct mali_stencil_packed stencil_back;
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u8 stencil_mask_front;
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u8 stencil_mask_back;
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};
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struct panfrost_sampler_state {
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struct pipe_sampler_state base;
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struct mali_sampler_descriptor midgard_hw;
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@ -1211,12 +1211,12 @@ panfrost_batch_set_requirements(struct panfrost_batch *batch)
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if (ctx->rasterizer && ctx->rasterizer->base.multisample)
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batch->requirements |= PAN_REQ_MSAA;
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if (ctx->depth_stencil && ctx->depth_stencil->depth.writemask) {
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if (ctx->depth_stencil && ctx->depth_stencil->base.depth.writemask) {
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batch->requirements |= PAN_REQ_DEPTH_WRITE;
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batch->draws |= PIPE_CLEAR_DEPTH;
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}
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if (ctx->depth_stencil && ctx->depth_stencil->stencil[0].enabled)
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if (ctx->depth_stencil && ctx->depth_stencil->base.stencil[0].enabled)
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batch->draws |= PIPE_CLEAR_STENCIL;
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}
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@ -170,7 +170,7 @@ panfrost_sfbd_set_zsbuf(
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fb->depth_stride = rsrc->slices[level].stride;
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/* No stencil? Job done. */
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if (!ctx->depth_stencil || !ctx->depth_stencil->stencil[0].enabled)
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if (!ctx->depth_stencil || !ctx->depth_stencil->base.stencil[0].enabled)
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return;
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if (panfrost_is_z24s8_variant(surf->format)) {
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@ -311,9 +311,6 @@ typedef struct compiler_context {
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/* Count of instructions emitted from NIR overall, across all blocks */
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int instruction_count;
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/* Alpha ref value passed in */
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float alpha_ref;
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unsigned quadword_count;
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/* Bitmask of valid metadata */
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@ -2847,7 +2847,6 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
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ctx->nir = nir;
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ctx->stage = nir->info.stage;
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ctx->is_blend = is_blend;
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ctx->alpha_ref = program->alpha_ref;
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ctx->blend_rt = MIDGARD_COLOR_RT0 + blend_rt;
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ctx->blend_input = ~0;
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ctx->blend_src1 = ~0;
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@ -107,9 +107,6 @@ typedef struct {
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* (register spilling), or zero if no spilling is used */
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unsigned tls_size;
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/* IN: For a fragment shader with a lowered alpha test, the ref value */
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float alpha_ref;
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/* IN: Render target formats for output load/store lowering */
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enum pipe_format rt_formats[8];
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} panfrost_program;
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