radv/tess: drop tcs_in_layout setting completely.
Inline all calcs at shader creation. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -65,7 +65,6 @@ struct radv_shader_context {
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LLVMValueRef tcs_offchip_layout;
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LLVMValueRef tcs_out_offsets;
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LLVMValueRef tcs_out_layout;
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LLVMValueRef tcs_in_layout;
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LLVMValueRef oc_lds;
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LLVMValueRef merged_wave_info;
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LLVMValueRef tess_factor_offset;
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@ -108,6 +107,7 @@ struct radv_shader_context {
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uint32_t tcs_patch_outputs_read;
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uint64_t tcs_outputs_read;
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uint32_t tcs_vertices_per_patch;
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uint32_t tcs_num_inputs;
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};
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enum radeon_llvm_calling_convention {
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@ -162,7 +162,11 @@ static LLVMValueRef
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get_tcs_in_patch_stride(struct radv_shader_context *ctx)
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{
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assert (ctx->stage == MESA_SHADER_TESS_CTRL);
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return ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 0, 13);
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uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
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uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
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input_patch_size /= 4;
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return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
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}
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static LLVMValueRef
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@ -462,7 +466,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx,
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if (previous_stage == MESA_SHADER_VERTEX)
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user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
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}
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user_sgpr_info->sgpr_count += 4;
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user_sgpr_info->sgpr_count += 3;
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break;
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case MESA_SHADER_TESS_EVAL:
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user_sgpr_info->sgpr_count += 1;
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@ -764,8 +768,6 @@ static void create_function(struct radv_shader_context *ctx,
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&ctx->tcs_out_offsets);
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->tcs_out_layout);
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->tcs_in_layout);
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if (needs_view_index)
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->abi.view_index);
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@ -789,8 +791,6 @@ static void create_function(struct radv_shader_context *ctx,
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&ctx->tcs_out_offsets);
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->tcs_out_layout);
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->tcs_in_layout);
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if (needs_view_index)
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add_arg(&args, ARG_SGPR, ctx->ac.i32,
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&ctx->abi.view_index);
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@ -999,7 +999,7 @@ static void create_function(struct radv_shader_context *ctx,
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case MESA_SHADER_TESS_CTRL:
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set_vs_specific_input_locs(ctx, stage, has_previous_stage,
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previous_stage, &user_sgpr_idx);
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set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 4);
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set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, &user_sgpr_idx, 3);
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if (ctx->abi.view_index)
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set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
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break;
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@ -1226,7 +1226,8 @@ load_tcs_varyings(struct ac_shader_abi *abi,
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unsigned param = shader_io_get_unique_index(location);
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if (load_input) {
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stride = ac_unpack_param(&ctx->ac, ctx->tcs_in_layout, 13, 8);
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uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
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stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
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dw_addr = get_tcs_in_current_patch_offset(ctx);
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} else {
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if (!is_patch) {
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@ -3019,6 +3020,10 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
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ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
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ctx.abi.store_tcs_outputs = store_tcs_output;
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ctx.tcs_vertices_per_patch = shaders[i]->info.tess.tcs_vertices_out;
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if (shader_count == 1)
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ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
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else
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ctx.tcs_num_inputs = util_last_bit64(shader_info->info.vs.ls_outputs_written);
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} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
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ctx.tes_primitive_mode = shaders[i]->info.tess.primitive_mode;
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ctx.abi.load_tess_varyings = load_tes_input;
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@ -3092,8 +3097,11 @@ LLVMModuleRef ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
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} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
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shader_info->tcs.outputs_written = ctx.tess_outputs_written;
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shader_info->tcs.patch_outputs_written = ctx.tess_patch_outputs_written;
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assert(ctx.tess_outputs_written == ctx.shader_info->info.tcs.outputs_written);
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assert(ctx.tess_patch_outputs_written == ctx.shader_info->info.tcs.patch_outputs_written);
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} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && ctx.options->key.vs.as_ls) {
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shader_info->vs.outputs_written = ctx.tess_outputs_written;
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assert(ctx.tess_outputs_written == ctx.shader_info->info.vs.ls_outputs_written);
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}
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}
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@ -62,7 +62,6 @@ struct radv_blend_state {
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struct radv_tessellation_state {
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uint32_t ls_hs_config;
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uint32_t tcs_in_layout;
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uint32_t tcs_out_layout;
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uint32_t tcs_out_offsets;
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uint32_t offchip_layout;
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@ -1383,8 +1382,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
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tess.lds_size = lds_size;
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tess.tcs_in_layout = (input_patch_size / 4) |
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((input_vertex_size / 4) << 13);
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tess.tcs_out_layout = (output_patch_size / 4) |
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((output_vertex_size / 4) << 13);
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tess.tcs_out_offsets = (output_patch0_offset / 16) |
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@ -1597,6 +1594,7 @@ radv_fill_shader_keys(struct radv_shader_variant_key *keys,
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if (nir[MESA_SHADER_TESS_CTRL]) {
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keys[MESA_SHADER_VERTEX].vs.as_ls = true;
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keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
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keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
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keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
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@ -1811,6 +1809,9 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
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for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
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if(modules[i] && !pipeline->shaders[i]) {
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if (i == MESA_SHADER_TESS_CTRL) {
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keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
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}
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pipeline->shaders[i] = radv_shader_variant_create(device, modules[i], &nir[i], 1,
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pipeline->layout,
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keys + i, &codes[i],
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@ -2614,13 +2615,12 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs,
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loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
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if (loc->sgpr_idx != -1) {
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uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
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assert(loc->num_sgprs == 4);
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assert(loc->num_sgprs == 3);
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assert(!loc->indirect);
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radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
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radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 3);
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radeon_emit(cs, tess->offchip_layout);
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radeon_emit(cs, tess->tcs_out_offsets);
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radeon_emit(cs, tess->tcs_out_layout);
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radeon_emit(cs, tess->tcs_in_layout);
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}
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loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
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@ -69,6 +69,7 @@ struct radv_tcs_variant_key {
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struct radv_vs_variant_key vs_key;
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unsigned primitive_mode;
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unsigned input_vertices;
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unsigned num_inputs;
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uint32_t tes_reads_tess_factors:1;
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};
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