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r600: rework cb/db setup 

Setup the regs when we emit rather than during state setup.
In certain cases a proper CB target was never emitted.
This fixes bug 23658.
This commit is contained in:
Alex Deucher 2009-09-03 18:02:54 -04:00
parent 323440b3e2
commit 6a97cca081
3 changed files with 107 additions and 128 deletions
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91
src/mesa/drivers/dri/r600/r700_chip.c
View File

@ -265,6 +265,93 @@ static void r700SendVTXState(GLcontext *ctx, struct radeon_state_atom *atom)
}
}
static void r700SetRenderTarget(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
rrb = radeon_get_colorbuffer(&context->radeon);
if (!rrb || !rrb->bo) {
return;
}
R600_STATECHANGE(context, cb_target);
/* color buffer */
r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
nPitchInPixel = rrb->pitch/rrb->cpp;
SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
if(4 == rrb->cpp)
{
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
}
else
{
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
COMP_SWAP_shift, COMP_SWAP_mask);
}
SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
r700->render_target[id].enabled = GL_TRUE;
}
static void r700SetDepthTarget(context_t *context)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
rrb = radeon_get_depthbuffer(&context->radeon);
if (!rrb)
return;
R600_STATECHANGE(context, db_target);
/* depth buf */
r700->DB_DEPTH_SIZE.u32All = 0;
r700->DB_DEPTH_BASE.u32All = 0;
r700->DB_DEPTH_INFO.u32All = 0;
r700->DB_DEPTH_VIEW.u32All = 0;
nPitchInPixel = rrb->pitch/rrb->cpp;
SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
if(4 == rrb->cpp)
{
SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
}
else
{
SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
}
SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
/* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
}
static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *atom)
{
context_t *context = R700_CONTEXT(ctx);
@ -279,6 +366,8 @@ static void r700SendDepthTargetState(GLcontext *ctx, struct radeon_state_atom *a
return;
}
r700SetDepthTarget(context);
BEGIN_BATCH_NO_AUTOSTATE(8 + 2);
R600_OUT_BATCH_REGSEQ(DB_DEPTH_SIZE, 2);
R600_OUT_BATCH(r700->DB_DEPTH_SIZE.u32All);
@ -319,6 +408,8 @@ static void r700SendRenderTargetState(GLcontext *ctx, struct radeon_state_atom *
return;
}
r700SetRenderTarget(context, 0);
if (id > R700_MAX_RENDER_TARGETS)
return;

141
src/mesa/drivers/dri/r600/r700_state.c
View File

@ -60,13 +60,6 @@ static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
static void r700UpdatePolygonMode(GLcontext * ctx);
static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
static void r700SetStencilState(GLcontext * ctx, GLboolean state);
static void r700SetRenderTarget(context_t *context, int id);
static void r700SetDepthTarget(context_t *context);
void r700SetDefaultStates(context_t *context) //--------------------
{
}
void r700UpdateShaders (GLcontext * ctx) //----------------------------------
{
@ -133,21 +126,6 @@ void r700UpdateViewportOffset(GLcontext * ctx) //------------------
radeonUpdateScissor(ctx);
}
/**
* Tell the card where to render (offset, pitch).
* Effected by glDrawBuffer, etc
*/
void r700UpdateDrawBuffer(GLcontext * ctx) /* TODO */ //---------------------
{
context_t *context = R700_CONTEXT(ctx);
R600_STATECHANGE(context, cb_target);
R600_STATECHANGE(context, db_target);
r700SetRenderTarget(context, 0);
r700SetDepthTarget(context);
}
void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state) //--------------------
{
struct r700_fragment_program *fp =
@ -179,21 +157,21 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-----------
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
_swrast_InvalidateState(ctx, new_state);
_swsetup_InvalidateState(ctx, new_state);
_vbo_InvalidateState(ctx, new_state);
_tnl_InvalidateState(ctx, new_state);
_ae_invalidate_state(ctx, new_state);
_swsetup_InvalidateState(ctx, new_state);
_vbo_InvalidateState(ctx, new_state);
_tnl_InvalidateState(ctx, new_state);
_ae_invalidate_state(ctx, new_state);
if (new_state & (_NEW_BUFFERS | _NEW_COLOR | _NEW_PIXEL))
{
_mesa_update_framebuffer(ctx);
/* this updates the DrawBuffer's Width/Height if it's a FBO */
_mesa_update_draw_buffer_bounds(ctx);
if (new_state & _NEW_BUFFERS) {
_mesa_update_framebuffer(ctx);
/* this updates the DrawBuffer's Width/Height if it's a FBO */
_mesa_update_draw_buffer_bounds(ctx);
r700UpdateDrawBuffer(ctx);
}
R600_STATECHANGE(context, cb_target);
R600_STATECHANGE(context, db_target);
}
r700UpdateStateParameters(ctx, new_state);
r700UpdateStateParameters(ctx, new_state);
R600_STATECHANGE(context, cl);
R600_STATECHANGE(context, spi);
@ -1373,97 +1351,6 @@ void r700SetScissor(context_t *context) //---------------
r700->viewport[id].enabled = GL_TRUE;
}
static void r700SetRenderTarget(context_t *context, int id)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
rrb = radeon_get_colorbuffer(&context->radeon);
if (!rrb || !rrb->bo) {
return;
}
R600_STATECHANGE(context, cb_target);
R600_STATECHANGE(context, cb);
/* screen/window/view */
SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
/* color buffer */
r700->render_target[id].CB_COLOR0_BASE.u32All = context->radeon.state.color.draw_offset;
nPitchInPixel = rrb->pitch/rrb->cpp;
SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, (nPitchInPixel/8)-1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
SETfield(r700->render_target[id].CB_COLOR0_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
r700->render_target[id].CB_COLOR0_BASE.u32All = 0;
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, ARRAY_LINEAR_GENERAL,
CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
if(4 == rrb->cpp)
{
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_8_8_8_8,
CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT, COMP_SWAP_shift, COMP_SWAP_mask);
}
else
{
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, COLOR_5_6_5,
CB_COLOR0_INFO__FORMAT_shift, CB_COLOR0_INFO__FORMAT_mask);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, SWAP_ALT_REV,
COMP_SWAP_shift, COMP_SWAP_mask);
}
SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, SOURCE_FORMAT_bit);
SETbit(r700->render_target[id].CB_COLOR0_INFO.u32All, BLEND_CLAMP_bit);
SETfield(r700->render_target[id].CB_COLOR0_INFO.u32All, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
r700->render_target[id].enabled = GL_TRUE;
}
static void r700SetDepthTarget(context_t *context)
{
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
struct radeon_renderbuffer *rrb;
unsigned int nPitchInPixel;
rrb = radeon_get_depthbuffer(&context->radeon);
if (!rrb)
return;
R600_STATECHANGE(context, db_target);
/* depth buf */
r700->DB_DEPTH_SIZE.u32All = 0;
r700->DB_DEPTH_BASE.u32All = 0;
r700->DB_DEPTH_INFO.u32All = 0;
r700->DB_DEPTH_VIEW.u32All = 0;
nPitchInPixel = rrb->pitch/rrb->cpp;
SETfield(r700->DB_DEPTH_SIZE.u32All, (nPitchInPixel/8)-1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
SETfield(r700->DB_DEPTH_SIZE.u32All, ( (nPitchInPixel * context->radeon.radeonScreen->driScreen->fbHeight)/64 )-1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask); /* size in pixel / 64 - 1 */
if(4 == rrb->cpp)
{
SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_8_24,
DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
}
else
{
SETfield(r700->DB_DEPTH_INFO.u32All, DEPTH_16,
DB_DEPTH_INFO__FORMAT_shift, DB_DEPTH_INFO__FORMAT_mask);
}
SETfield(r700->DB_DEPTH_INFO.u32All, ARRAY_2D_TILED_THIN1,
DB_DEPTH_INFO__ARRAY_MODE_shift, DB_DEPTH_INFO__ARRAY_MODE_mask);
/* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
}
static void r700InitSQConfig(GLcontext * ctx)
{
context_t *context = R700_CONTEXT(ctx);
@ -1666,6 +1553,7 @@ void r700InitState(GLcontext * ctx) //-------------------
{
context_t *context = R700_CONTEXT(ctx);
R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
int id = 0;
radeon_firevertices(&context->radeon);
@ -1859,6 +1747,9 @@ void r700InitState(GLcontext * ctx) //-------------------
/* Set up color compare mask */
r700->CB_CLRCMP_MSK.u32All = 0xFFFFFFFF;
/* screen/window/view */
SETfield(r700->CB_TARGET_MASK.u32All, 0xF, (4 * id), TARGET0_ENABLE_mask);
context->radeon.hw.all_dirty = GL_TRUE;
}

3
src/mesa/drivers/dri/r600/r700_state.h
View File

@ -37,13 +37,10 @@ extern void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state);
extern void r700UpdateShaders (GLcontext * ctx);
extern void r700UpdateViewportOffset(GLcontext * ctx);
extern void r700UpdateDrawBuffer (GLcontext * ctx);
extern void r700InitState (GLcontext * ctx);
extern void r700InitStateFuncs (struct dd_function_table *functions);
extern void r700SetDefaultStates(context_t * context);
extern void r700SetScissor(context_t *context);
#endif /* _R600_SCREEN_H */