freedreno/compiler/a3xx: remove lowered instructions
Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
0f2df4ff90
commit
69eca28dd0
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@ -418,20 +418,6 @@ get_internal_temp_hr(struct fd3_compile_context *ctx,
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return tmp_src;
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}
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/* same as get_internal_temp, but w/ src.xxxx (for instructions that
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* replicate their results)
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*/
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static struct tgsi_src_register *
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get_internal_temp_repl(struct fd3_compile_context *ctx,
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struct tgsi_dst_register *tmp_dst)
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{
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struct tgsi_src_register *tmp_src =
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get_internal_temp(ctx, tmp_dst);
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tmp_src->SwizzleX = tmp_src->SwizzleY =
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tmp_src->SwizzleZ = tmp_src->SwizzleW = TGSI_SWIZZLE_X;
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return tmp_src;
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}
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static inline bool
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is_const(struct tgsi_src_register *src)
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{
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@ -706,227 +692,6 @@ vectorize(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
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* native instructions:
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*/
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/* LIT - Light Coefficients:
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* dst.x = 1.0
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* dst.y = max(src.x, 0.0)
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* dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0.0
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* dst.w = 1.0
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*
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* max.f tmp.y, src.y, {0.0}
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* nop
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* max.f tmp.z, src.w, {-128.0}
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* cmps.f.ge tmp.w, (neg)src.x, {0.0}
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* max.f dst.y, src.x, {0.0}
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* nop
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* min.f tmp.x, tmp.z, {128.0}
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* add.s tmp.z, tmp.w, -1
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* log2 tmp.y, tmp.y
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* (rpt1)nop
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* (ss)mul.f tmp.x, tmp.x, tmp.y
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* mov.f16f16 dst.x, {1.0}
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* mov.f16f16 dst.w, {1.0}
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* (rpt3)nop
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* exp2 tmp.x, tmp.x
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* (ss)sel.f16 dst.z, {0.0}, tmp.z, tmp.x
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*/
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static void
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trans_lit(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct ir3_register *r;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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struct tgsi_src_register constval0, constval1, constval128;
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struct tgsi_src_register *src = &inst->Src[0].Register;
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
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if (is_const(src))
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src = get_unconst(ctx, src);
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get_immediate(ctx, &constval0, fui(0.0));
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get_immediate(ctx, &constval1, fui(1.0));
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get_immediate(ctx, &constval128, fui(128.0));
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/* max.f tmp.y, src.y, {0.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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/* nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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/* max.f tmp.z, src.w, {-128.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_W);
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add_src_reg(ctx, instr, &constval128,
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constval128.SwizzleX)->flags |= IR3_REG_NEGATE;
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/* cmps.f.ge tmp.w, (neg)src.x, {0.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_W);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_X)->flags |= IR3_REG_NEGATE;
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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instr->cat2.condition = IR3_COND_GE;
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/* max.f dst.y, src.x, {0.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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/* nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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/* min.f tmp.x, tmp.z, {128.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MIN_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, &constval128, constval128.SwizzleX);
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/* add.s tmp.z, tmp.w, -1 */
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_W);
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ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
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/* log2 tmp.y, tmp.y */
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instr = ir3_instr_create(ctx->ir, 4, OPC_LOG2);
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r = add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Y);
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regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_Y);
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/* (rpt1)nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 1;
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/* (ss)mul.f tmp.x, tmp.x, tmp.y */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Y);
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/* mov.f16f16 dst.x, {1.0} */
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instr = ir3_instr_create(ctx->ir, 1, 0);
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instr->cat1.src_type = get_ftype(ctx);
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instr->cat1.dst_type = get_ftype(ctx);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, &constval1, constval1.SwizzleX);
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/* mov.f16f16 dst.w, {1.0} */
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instr = ir3_instr_create(ctx->ir, 1, 0);
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instr->cat1.src_type = get_ftype(ctx);
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instr->cat1.dst_type = get_ftype(ctx);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_W);
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add_src_reg(ctx, instr, &constval1, constval1.SwizzleX);
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/* (rpt3)nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 3;
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/* exp2 tmp.x, tmp.x */
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instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
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r = add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
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/* (ss)sel.f16 dst.z, {0.0}, tmp.z, tmp.x */
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instr = ir3_instr_create(ctx->ir, 3,
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ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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put_dst(ctx, inst, dst);
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}
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static inline void
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get_swiz(unsigned *swiz, struct tgsi_src_register *src)
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{
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swiz[0] = src->SwizzleX;
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swiz[1] = src->SwizzleY;
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swiz[2] = src->SwizzleZ;
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swiz[3] = src->SwizzleW;
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}
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static void
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trans_dotp(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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struct tgsi_dst_register *dst = &inst->Dst[0].Register;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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unsigned swiz0[4];
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unsigned swiz1[4];
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opc_t opc_mad = ctx->so->half_precision ? OPC_MAD_F16 : OPC_MAD_F32;
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unsigned n = t->arg; /* number of components */
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unsigned i, swapped = 0;
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tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
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/* in particular, can't handle const for src1 for cat3/mad:
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*/
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if (is_rel_or_const(src1)) {
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if (!is_rel_or_const(src0)) {
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struct tgsi_src_register *tmp;
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tmp = src0;
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src0 = src1;
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src1 = tmp;
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swapped = 1;
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} else {
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src0 = get_unconst(ctx, src0);
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}
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}
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get_swiz(swiz0, src0);
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get_swiz(swiz1, src1);
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src0, swiz0[0]);
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add_src_reg(ctx, instr, src1, swiz1[0]);
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for (i = 1; i < n; i++) {
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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instr = ir3_instr_create(ctx->ir, 3, opc_mad);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src0, swiz0[i]);
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add_src_reg(ctx, instr, src1, swiz1[i]);
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add_src_reg(ctx, instr, tmp_src, 0);
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}
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/* DPH(a,b) = (a.x * b.x) + (a.y * b.y) + (a.z * b.z) + b.w */
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if (t->tgsi_opc == TGSI_OPCODE_DPH) {
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 1;
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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if (swapped)
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add_src_reg(ctx, instr, src0, swiz0[i]);
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else
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add_src_reg(ctx, instr, src1, swiz1[i]);
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add_src_reg(ctx, instr, tmp_src, 0);
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n++;
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}
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 2;
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/* because of get_internal_temp_repl(), this will replicate
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* the results to all components of dst:
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*/
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create_mov(ctx, dst, tmp_src);
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}
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static void
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trans_clamp(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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@ -942,73 +707,6 @@ trans_clamp(const struct instr_translater *t,
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put_dst(ctx, inst, dst);
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}
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/* LRP(a,b,c) = (a * b) + ((1 - a) * c) */
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static void
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trans_lrp(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst1, tmp_dst2;
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struct tgsi_src_register *tmp_src1, *tmp_src2;
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struct tgsi_src_register tmp_const;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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if (is_const(src0) && is_const(src1))
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src0 = get_unconst(ctx, src0);
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tmp_src1 = get_internal_temp(ctx, &tmp_dst1);
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tmp_src2 = get_internal_temp(ctx, &tmp_dst2);
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get_immediate(ctx, &tmp_const, fui(1.0));
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/* tmp1 = (a * b) */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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vectorize(ctx, instr, &tmp_dst1, 2, src0, 0, src1, 0);
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/* tmp2 = (1 - a) */
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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vectorize(ctx, instr, &tmp_dst2, 2, &tmp_const, 0,
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src0, IR3_REG_NEGATE);
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/* tmp2 = tmp2 * c */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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vectorize(ctx, instr, &tmp_dst2, 2,
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tmp_src2, 0,
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&inst->Src[2].Register, 0);
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/* dst = tmp1 + tmp2 */
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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vectorize(ctx, instr, &inst->Dst[0].Register, 2,
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tmp_src1, 0,
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tmp_src2, 0);
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}
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/* FRC(x) = x - FLOOR(x) */
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static void
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trans_frac(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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tmp_src = get_internal_temp(ctx, &tmp_dst);
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/* tmp = FLOOR(x) */
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instr = ir3_instr_create(ctx->ir, 2, OPC_FLOOR_F);
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vectorize(ctx, instr, &tmp_dst, 1,
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&inst->Src[0].Register, 0);
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/* dst = x - tmp */
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_F);
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vectorize(ctx, instr, &inst->Dst[0].Register, 2,
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&inst->Src[0].Register, 0,
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tmp_src, IR3_REG_NEGATE);
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}
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/* ARL(x) = x, but mova from hrN.x to a0.. */
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static void
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trans_arl(const struct instr_translater *t,
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@ -1055,50 +753,6 @@ trans_arl(const struct instr_translater *t,
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
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}
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/* POW(a,b) = EXP2(b * LOG2(a)) */
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static void
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trans_pow(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct ir3_register *r;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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struct tgsi_dst_register *dst = &inst->Dst[0].Register;
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struct tgsi_src_register *src0 = &inst->Src[0].Register;
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struct tgsi_src_register *src1 = &inst->Src[1].Register;
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tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
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/* log2 Rtmp, Rsrc0 */
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
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instr = ir3_instr_create(ctx->ir, 4, OPC_LOG2);
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r = add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, src0, src0->SwizzleX);
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regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
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/* mul.f Rtmp, Rtmp, Rsrc1 */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, tmp_src, 0);
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add_src_reg(ctx, instr, src1, src1->SwizzleX);
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/* blob compiler seems to ensure there are at least 6 instructions
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* between a "simple" (non-cat4) instruction and a dependent cat4..
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* probably we need to handle this in some other places too.
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*/
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 5;
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/* exp2 Rdst, Rtmp */
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instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
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r = add_dst_reg(ctx, instr, &tmp_dst, 0);
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add_src_reg(ctx, instr, tmp_src, 0);
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regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
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create_mov(ctx, dst, tmp_src);
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}
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/* texture fetch/sample instructions: */
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static void
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trans_samp(const struct instr_translater *t,
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@ -1591,30 +1245,22 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
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[TGSI_OPCODE_ ## n] = { .fxn = (f), .tgsi_opc = TGSI_OPCODE_ ## n, ##__VA_ARGS__ }
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INSTR(MOV, instr_cat1),
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INSTR(LIT, trans_lit),
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INSTR(RCP, instr_cat4, .opc = OPC_RCP),
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INSTR(RSQ, instr_cat4, .opc = OPC_RSQ),
|
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INSTR(SQRT, instr_cat4, .opc = OPC_SQRT),
|
||||
INSTR(MUL, instr_cat2, .opc = OPC_MUL_F),
|
||||
INSTR(ADD, instr_cat2, .opc = OPC_ADD_F),
|
||||
INSTR(SUB, instr_cat2, .opc = OPC_ADD_F),
|
||||
INSTR(DP2, trans_dotp, .arg = 2),
|
||||
INSTR(DP3, trans_dotp, .arg = 3),
|
||||
INSTR(DP4, trans_dotp, .arg = 4),
|
||||
INSTR(DPH, trans_dotp, .arg = 3), /* almost like DP3 */
|
||||
INSTR(MIN, instr_cat2, .opc = OPC_MIN_F),
|
||||
INSTR(MAX, instr_cat2, .opc = OPC_MAX_F),
|
||||
INSTR(MAD, instr_cat3, .opc = OPC_MAD_F32, .hopc = OPC_MAD_F16),
|
||||
INSTR(TRUNC, instr_cat2, .opc = OPC_TRUNC_F),
|
||||
INSTR(LRP, trans_lrp),
|
||||
INSTR(FRC, trans_frac),
|
||||
INSTR(CLAMP, trans_clamp),
|
||||
INSTR(FLR, instr_cat2, .opc = OPC_FLOOR_F),
|
||||
INSTR(ROUND, instr_cat2, .opc = OPC_RNDNE_F),
|
||||
INSTR(ARL, trans_arl),
|
||||
INSTR(EX2, instr_cat4, .opc = OPC_EXP2),
|
||||
INSTR(LG2, instr_cat4, .opc = OPC_LOG2),
|
||||
INSTR(POW, trans_pow),
|
||||
INSTR(ABS, instr_cat2, .opc = OPC_ABSNEG_F),
|
||||
INSTR(COS, instr_cat4, .opc = OPC_COS),
|
||||
INSTR(SIN, instr_cat4, .opc = OPC_SIN),
|
||||
|
|
|
|||
Loading…
Reference in New Issue