From 694731ac13b5c3469d7504e909dae0da3ace2fc3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Wed, 15 Sep 2021 15:28:46 -0400
Subject: [PATCH] ac/surface: allow gfx6-8 to enter the gfx9 DCC codepath for
 SI_FORCE_FAMILY

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13871>
---
 src/amd/common/ac_surface.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 6448407594a..20942a0120c 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1529,6 +1529,11 @@ static bool is_dcc_supported_by_DCN(const struct radeon_info *info,
       return false;
 
    switch (info->chip_class) {
+   case GFX6:
+   case GFX7:
+   case GFX8:
+      /* We can get here due to SI_FORCE_FAMILY. */
+      return false;
    case GFX9:
       /* There are more constraints, but we always set
        * INDEPENDENT_64B_BLOCKS = 1 and MAX_COMPRESSED_BLOCK_SIZE = 64B,