radv: emit vertex shader to correct hw block.
This emits the shader to the ES block in the correct case. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -516,6 +516,22 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
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S_028AB4_REUSE_OFF(shader->info.vs.writes_viewport_index));
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S_028AB4_REUSE_OFF(shader->info.vs.writes_viewport_index));
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}
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}
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static void
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radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
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struct radv_shader_variant *shader)
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{
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struct radeon_winsys *ws = cmd_buffer->device->ws;
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uint64_t va = ws->buffer_get_va(shader->bo);
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ws->cs_add_buffer(cmd_buffer->cs, shader->bo, 8);
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radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
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radeon_emit(cmd_buffer->cs, va >> 8);
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radeon_emit(cmd_buffer->cs, va >> 40);
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radeon_emit(cmd_buffer->cs, shader->rsrc1);
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radeon_emit(cmd_buffer->cs, shader->rsrc2);
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}
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static void
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static void
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radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
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radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
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struct radv_pipeline *pipeline)
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struct radv_pipeline *pipeline)
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@ -526,7 +542,10 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
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vs = pipeline->shaders[MESA_SHADER_VERTEX];
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vs = pipeline->shaders[MESA_SHADER_VERTEX];
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radv_emit_hw_vs(cmd_buffer, pipeline, vs);
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if (vs->info.vs.as_es)
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radv_emit_hw_es(cmd_buffer, vs);
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else
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radv_emit_hw_vs(cmd_buffer, pipeline, vs);
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radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
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radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, 0);
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}
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}
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