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freedreno/registers: Rename SP_2D_SRC_FORMAT 

This register contains information about the destination format, so
let's rename to SP_2D_DST_FORMAT.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5717>
This commit is contained in:
Kristian H. Kristensen 2020-07-13 20:06:25 -07:00 committed by Marge Bot
parent d5c82c3c5f
commit 684cfca748
4 changed files with 13 additions and 16 deletions
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5
src/freedreno/registers/a6xx.xml
View File

@ -3217,10 +3217,7 @@ to upconvert to 32b float internally?
<reg32 offset="0xab1b" name="SP_IBO_HI"/>
<reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
<!--
not really src, COLOR_FORMAT/SRGB seem to be related to ifmt which is for dst
-->
<reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT">
<bitfield name="NORM" pos="0" type="boolean"/>
<bitfield name="SINT" pos="1" type="boolean"/>
<bitfield name="UINT" pos="2" type="boolean"/>

2
src/freedreno/vulkan/tu_clear_blit.c
View File

@ -288,7 +288,7 @@ r2d_setup_common(struct tu_cmd_buffer *cmd,
if (format == FMT6_10_10_10_2_UNORM_DEST)
format = FMT6_16_16_16_16_FLOAT;
tu_cs_emit_regs(cs, A6XX_SP_2D_SRC_FORMAT(
tu_cs_emit_regs(cs, A6XX_SP_2D_DST_FORMAT(
.sint = vk_format_is_sint(vk_format),
.uint = vk_format_is_uint(vk_format),
.color_format = format,

20
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
View File

@ -267,21 +267,21 @@ emit_blit_setup(struct fd_ringbuffer *ring,
* controlling the internal/accumulator format or something like
* that. It's certainly not tied to only the src format.
*/
OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
OUT_RING(ring, A6XX_SP_2D_SRC_FORMAT_COLOR_FORMAT(fmt) |
OUT_PKT4(ring, REG_A6XX_SP_2D_DST_FORMAT, 1);
OUT_RING(ring, A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(fmt) |
COND(util_format_is_pure_sint(pfmt),
A6XX_SP_2D_SRC_FORMAT_SINT) |
A6XX_SP_2D_DST_FORMAT_SINT) |
COND(util_format_is_pure_uint(pfmt),
A6XX_SP_2D_SRC_FORMAT_UINT) |
A6XX_SP_2D_DST_FORMAT_UINT) |
COND(util_format_is_snorm(pfmt),
A6XX_SP_2D_SRC_FORMAT_SINT |
A6XX_SP_2D_SRC_FORMAT_NORM) |
A6XX_SP_2D_DST_FORMAT_SINT |
A6XX_SP_2D_DST_FORMAT_NORM) |
COND(util_format_is_unorm(pfmt),
// TODO sometimes blob uses UINT+NORM but dEQP seems unhappy about that
// A6XX_SP_2D_SRC_FORMAT_UINT |
A6XX_SP_2D_SRC_FORMAT_NORM) |
COND(is_srgb, A6XX_SP_2D_SRC_FORMAT_SRGB) |
A6XX_SP_2D_SRC_FORMAT_MASK(0xf));
// A6XX_SP_2D_DST_FORMAT_UINT |
A6XX_SP_2D_DST_FORMAT_NORM) |
COND(is_srgb, A6XX_SP_2D_DST_FORMAT_SRGB) |
A6XX_SP_2D_DST_FORMAT_MASK(0xf));
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
OUT_RING(ring, 0);

2
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
View File

@ -382,7 +382,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
OUT_PKT4(ring, REG_A6XX_SP_2D_DST_FORMAT, 1);
OUT_RING(ring, 0x0000f410);
OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);