freedreno/ir3: add post-scheduler cp pass
A pass to eliminate extra mov's from an array. We need to do this after scheduling so we know that there are not any potentially conflicting array writes between the original `mov` and it's use(s). Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2124 Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5280>
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@ -28,6 +28,7 @@ ir3_SOURCES := \
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ir3/ir3_context.c \
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ir3/ir3_context.h \
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ir3/ir3_cp.c \
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ir3/ir3_cp_postsched.c \
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ir3/ir3_cf.c \
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ir3/ir3_dce.c \
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ir3/ir3_delay.c \
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@ -1304,6 +1304,7 @@ bool ir3_cf(struct ir3 *ir);
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/* copy-propagate: */
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bool ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so);
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bool ir3_cp_postsched(struct ir3 *ir);
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/* group neighbors and insert mov's to resolve conflicts: */
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bool ir3_group(struct ir3 *ir);
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@ -3639,6 +3639,11 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
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ir3_debug_print(ir, "AFTER: ir3_sched");
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if (IR3_PASS(ir, ir3_cp_postsched)) {
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/* cleanup the result of removing unneeded mov's: */
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while (IR3_PASS(ir, ir3_dce, so)) {}
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}
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/* Pre-assign VS inputs on a6xx+ binning pass shader, to align
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* with draw pass VS, so binning and draw pass can both use the
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* same VBO state.
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@ -0,0 +1,215 @@
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/*
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* Copyright © 2020 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "util/ralloc.h"
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#include "util/u_dynarray.h"
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#include "ir3.h"
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/**
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* A bit more extra cleanup after sched pass. In particular, prior to
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* instruction scheduling, we can't easily eliminate unneeded mov's
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* from "arrays", because we don't yet know if there is an intervening
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* array-write scheduled before the use of the array-read.
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*
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* NOTE array is equivalent to nir "registers".. ie. it can be length of
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* one. It is basically anything that is not SSA.
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*/
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/**
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* Check if any instruction before `use` and after `src` writes to the
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* specified array. If `offset` is negative, it is a relative (a0.x)
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* access and we care about all writes to the array (as we don't know
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* which array element is read). Otherwise in the case of non-relative
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* access, we only have to care about the write to the specified (>= 0)
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* offset.
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*/
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static bool
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has_conflicting_write(struct ir3_instruction *src,
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struct ir3_instruction *use,
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unsigned id, int offset)
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{
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assert(src->block == use->block);
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/* NOTE that since src and use are in the same block, src by
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* definition appears in the block's instr_list before use:
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*/
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foreach_instr_rev (instr, &use->node) {
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if (instr == src)
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break;
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/* if we are looking at a RELATIV read, we can't move
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* it past an a0.x write:
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*/
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if ((offset < 0) && (dest_regs(instr) > 0) &&
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(instr->regs[0]->num == regid(REG_A0, 0)))
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return true;
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if (!writes_gpr(instr))
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continue;
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struct ir3_register *dst = instr->regs[0];
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if (!(dst->flags & IR3_REG_ARRAY))
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continue;
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if (dst->array.id != id)
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continue;
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/*
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* At this point, we have narrowed down an instruction
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* that writes to the same array.. check if it the write
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* is to an array element that we care about:
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*/
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/* is write to an unknown array element? */
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if (dst->flags & IR3_REG_RELATIV)
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return true;
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/* is read from an unknown array element? */
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if (offset < 0)
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return true;
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/* is write to same array element? */
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if (dst->array.offset == offset)
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return true;
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}
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return false;
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}
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/* Can we fold the mov src into use without invalid flags? */
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static bool
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valid_flags(struct ir3_instruction *use, struct ir3_instruction *mov)
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{
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struct ir3_register *src = mov->regs[1];
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foreach_src_n (reg, n, use) {
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if (ssa(reg) != mov)
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continue;
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if (!ir3_valid_flags(use, n, reg->flags | src->flags))
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return false;
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}
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return true;
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}
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static bool
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instr_cp_postsched(struct ir3_instruction *mov)
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{
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struct ir3_register *src = mov->regs[1];
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/* only consider mov's from "arrays", other cases we have
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* already considered already:
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*/
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if (!(src->flags & IR3_REG_ARRAY))
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return false;
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int offset = (src->flags & IR3_REG_RELATIV) ? -1 : src->array.offset;
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/* Once we move the array read directly into the consuming
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* instruction(s), we will also need to update instructions
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* that had a false-dep on the original mov to have deps
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* on the consuming instructions:
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*/
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struct util_dynarray newdeps;
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util_dynarray_init(&newdeps, mov->uses);
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foreach_ssa_use (use, mov) {
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if (use->block != mov->block)
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continue;
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if (is_meta(use))
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continue;
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if (has_conflicting_write(mov, use, src->array.id, offset))
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continue;
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if (conflicts(mov->address, use->address))
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continue;
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if (!valid_flags(use, mov))
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continue;
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/* Ok, we've established that it is safe to remove this copy: */
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bool removed = false;
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foreach_src_n (reg, n, use) {
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if (ssa(reg) != mov)
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continue;
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use->regs[n + 1] = ir3_reg_clone(mov->block->shader, src);
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/* preserve (abs)/etc modifiers: */
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use->regs[n + 1]-> flags |= reg->flags;
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removed = true;
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}
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/* the use could have been only a false-dep, only add to
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* the newdeps array if we've actually updated a real
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* src reg for the use:
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*/
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if (removed) {
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util_dynarray_append(&newdeps, struct ir3_instruction *, use);
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/* Remove the use from the src instruction: */
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_mesa_set_remove_key(mov->uses, use);
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}
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}
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/* Once we have the complete set of instruction(s) that are are now
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* directly reading from the array, update any false-dep uses to
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* now depend on these instructions. The only remaining uses at
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* this point should be false-deps:
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*/
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foreach_ssa_use (use, mov) {
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util_dynarray_foreach(&newdeps, struct ir3_instruction *, instrp) {
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struct ir3_instruction *newdep = *instrp;
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ir3_instr_add_dep(use, newdep);
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}
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}
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return util_dynarray_num_elements(&newdeps, struct ir3_instruction **) > 0;
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}
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bool
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ir3_cp_postsched(struct ir3 *ir)
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{
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void *mem_ctx = ralloc_context(NULL);
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bool progress = false;
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ir3_find_ssa_uses(ir, mem_ctx, false);
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foreach_block (block, &ir->block_list) {
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foreach_instr_safe (instr, &block->instr_list) {
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if (is_same_type_mov(instr))
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progress |= instr_cp_postsched(instr);
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}
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}
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ralloc_free(mem_ctx);
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return progress;
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}
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@ -73,6 +73,7 @@ libfreedreno_ir3_files = files(
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'ir3_context.h',
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'ir3_cf.c',
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'ir3_cp.c',
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'ir3_cp_postsched.c',
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'ir3_dce.c',
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'ir3_delay.c',
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'ir3_group.c',
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