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i965: Don't force x-tiling for 16-bpp formats on Gen>7 

Sandybridge doesn't support y-tiling for surface formats with 16 or
more bpp. There was previously an override to explicitly allow this
for Gen7. However, this restriction is also removed in Gen8+ so we
should use y-tiling there too.

This is important to do for Skylake which doesn't support x-tiling for
3D surfaces.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
This commit is contained in:
Neil Roberts 2015-02-19 16:09:41 +00:00
parent 6d164f65c5
commit 67e3302497
1 changed files with 3 additions and 3 deletions
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6
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
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@ -515,10 +515,10 @@ intel_miptree_choose_tiling(struct brw_context *brw,
/* From the Sandybridge PRM, Volume 1, Part 2, page 32:
* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
* or Linear."
* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
* all the way back to 965, but is explicitly permitted on Gen7.
* 128 bits per pixel translates to 16 bytes per pixel. This is necessary
* all the way back to 965, but is permitted on Gen7+.
*/
if (brw->gen != 7 && mt->cpp >= 16)
if (brw->gen < 7 && mt->cpp >= 16)
return I915_TILING_X;
/* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most