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radeonsi: remove the unused cs parameter from remaining packet functions 

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13015>
This commit is contained in:
Marek Olšák 2021-09-23 07:17:58 -04:00 committed by Marge Bot
parent 0763bfdb95
commit 67bda8dc5f
3 changed files with 13 additions and 13 deletions
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10
src/gallium/drivers/radeonsi/si_build_pm4.h
View File

@ -152,7 +152,7 @@
radeon_emit(value); \
} while (0)
#define radeon_set_context_reg_rmw(cs, reg, value, mask) do { \
#define radeon_set_context_reg_rmw(reg, value, mask) do { \
SI_CHECK_SHADOWED_REGS(reg, 1); \
assert((reg) >= SI_CONTEXT_REG_OFFSET); \
radeon_emit(PKT3(PKT3_CONTEXT_REG_RMW, 2, 0)); \
@ -168,7 +168,7 @@
__value &= mask; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
radeon_set_context_reg_rmw(cs, offset, __value, mask); \
radeon_set_context_reg_rmw(offset, __value, mask); \
sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
} \
@ -279,7 +279,7 @@
} \
} while (0)
#define radeon_set_privileged_config_reg(cs, reg, value) do { \
#define radeon_set_privileged_config_reg(reg, value) do { \
assert((reg) < CIK_UCONFIG_REG_OFFSET); \
radeon_emit(PKT3(PKT3_COPY_DATA, 4, 0)); \
radeon_emit(COPY_DATA_SRC_SEL(COPY_DATA_IMM) | \
@ -290,7 +290,7 @@
radeon_emit(0); /* unused */ \
} while (0)
#define radeon_emit_32bit_pointer(sscreen, cs, va) do { \
#define radeon_emit_32bit_pointer(sscreen, va) do { \
radeon_emit(va); \
assert((va) == 0 || ((va) >> 32) == sscreen->info.address32_hi); \
} while (0)
@ -298,7 +298,7 @@
#define radeon_emit_one_32bit_pointer(sctx, desc, sh_base) do { \
unsigned sh_offset = (sh_base) + (desc)->shader_userdata_offset; \
radeon_set_sh_reg_seq(sh_offset, 1); \
radeon_emit_32bit_pointer(sctx->screen, cs, (desc)->gpu_address); \
radeon_emit_32bit_pointer(sctx->screen, (desc)->gpu_address); \
} while (0)
/* This should be evaluated at compile time if all parameters are constants. */

2
src/gallium/drivers/radeonsi/si_descriptors.c
View File

@ -2070,7 +2070,7 @@ void si_shader_change_notify(struct si_context *sctx)
\
radeon_set_sh_reg_seq(sh_offset, count); \
for (int i = 0; i < count; i++) \
radeon_emit_32bit_pointer(sctx->screen, cs, descs[i].gpu_address); \
radeon_emit_32bit_pointer(sctx->screen, descs[i].gpu_address); \
} \
} \
} while (0)

14
src/gallium/drivers/radeonsi/si_sqtt.c
View File

@ -104,20 +104,20 @@ si_emit_thread_trace_start(struct si_context* sctx,
if (sctx->chip_class >= GFX10) {
/* Order seems important for the following 2 registers. */
radeon_set_privileged_config_reg(cs, R_008D04_SQ_THREAD_TRACE_BUF0_SIZE,
radeon_set_privileged_config_reg(R_008D04_SQ_THREAD_TRACE_BUF0_SIZE,
S_008D04_SIZE(shifted_size) |
S_008D04_BASE_HI(shifted_va >> 32));
radeon_set_privileged_config_reg(cs, R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
radeon_set_privileged_config_reg(R_008D00_SQ_THREAD_TRACE_BUF0_BASE, shifted_va);
int wgp = first_active_cu / 2;
radeon_set_privileged_config_reg(cs, R_008D14_SQ_THREAD_TRACE_MASK,
radeon_set_privileged_config_reg(R_008D14_SQ_THREAD_TRACE_MASK,
S_008D14_WTYPE_INCLUDE(0x7f) | /* all shader stages */
S_008D14_SA_SEL(0) |
S_008D14_WGP_SEL(wgp) |
S_008D14_SIMD_SEL(0));
radeon_set_privileged_config_reg(cs, R_008D18_SQ_THREAD_TRACE_TOKEN_MASK,
radeon_set_privileged_config_reg(R_008D18_SQ_THREAD_TRACE_TOKEN_MASK,
S_008D18_REG_INCLUDE(V_008D18_REG_INCLUDE_SQDEC |
V_008D18_REG_INCLUDE_SHDEC |
V_008D18_REG_INCLUDE_GFXUDEC |
@ -127,7 +127,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
S_008D18_TOKEN_EXCLUDE(V_008D18_TOKEN_EXCLUDE_PERF));
/* Should be emitted last (it enables thread traces). */
radeon_set_privileged_config_reg(cs, R_008D1C_SQ_THREAD_TRACE_CTRL,
radeon_set_privileged_config_reg(R_008D1C_SQ_THREAD_TRACE_CTRL,
S_008D1C_MODE(1) |
S_008D1C_HIWATER(5) |
S_008D1C_UTIL_TIMER(1) |
@ -324,7 +324,7 @@ si_emit_thread_trace_stop(struct si_context *sctx,
radeon_emit(4); /* poll interval */
/* Disable the thread trace mode. */
radeon_set_privileged_config_reg(cs, R_008D1C_SQ_THREAD_TRACE_CTRL,
radeon_set_privileged_config_reg(R_008D1C_SQ_THREAD_TRACE_CTRL,
S_008D1C_MODE(0));
/* Wait for thread trace completion. */
@ -763,7 +763,7 @@ si_emit_spi_config_cntl(struct si_context* sctx,
radeon_set_uconfig_reg(R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
} else {
/* SPI_CONFIG_CNTL is a protected register on GFX6-GFX8. */
radeon_set_privileged_config_reg(cs, R_009100_SPI_CONFIG_CNTL,
radeon_set_privileged_config_reg(R_009100_SPI_CONFIG_CNTL,
S_009100_ENABLE_SQG_TOP_EVENTS(enable) |
S_009100_ENABLE_SQG_BOP_EVENTS(enable));
}