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radv/gfx10: fix required subgroup size with VK_EXT_subgroup_size_control 

If compute shaders require a specific subgroup size (ie. Wave32),
we have to return the correct one.

Fixes dEQP-VK.subgroups.size_control.compute.required_subgroup_size_*.

Fixes: fb07fd4e6c ("radv: implement VK_EXT_subgroup_size_control")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4215>
This commit is contained in:
Samuel Pitoiset 2020-03-16 17:29:33 +01:00 committed by Marge Bot
parent 46e8ba1344
commit 672d106199
3 changed files with 17 additions and 4 deletions
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13
src/amd/vulkan/radv_pipeline.c
View File

@ -2788,16 +2788,27 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
const VkPipelineShaderStageCreateInfo *stage = pStages[i];
unsigned subgroup_size = 64;
if (!modules[i])
continue;
radv_start_feedback(stage_feedbacks[i]);
if (key->compute_subgroup_size) {
/* Only GFX10+ and compute shaders currently support
* requiring a specific subgroup size.
*/
assert(device->physical_device->rad_info.chip_class >= GFX10 &&
i == MESA_SHADER_COMPUTE);
subgroup_size = key->compute_subgroup_size;
}
nir[i] = radv_shader_compile_to_nir(device, modules[i],
stage ? stage->pName : "main", i,
stage ? stage->pSpecializationInfo : NULL,
flags, pipeline->layout);
flags, pipeline->layout,
subgroup_size);
/* We don't want to alter meta shaders IR directly so clone it
* first.

5
src/amd/vulkan/radv_shader.c
View File

@ -292,7 +292,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
const VkPipelineCreateFlags flags,
const struct radv_pipeline_layout *layout)
const struct radv_pipeline_layout *layout,
unsigned subgroup_size)
{
nir_shader *nir;
const nir_shader_compiler_options *nir_options =
@ -481,7 +482,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
nir_remove_dead_variables(nir, nir_var_function_temp);
bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7;
nir_lower_subgroups(nir, &(struct nir_lower_subgroups_options) {
.subgroup_size = 64,
.subgroup_size = subgroup_size,
.ballot_bit_size = 64,
.lower_to_scalar = 1,
.lower_subgroup_masks = 1,

3
src/amd/vulkan/radv_shader.h
View File

@ -403,7 +403,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
gl_shader_stage stage,
const VkSpecializationInfo *spec_info,
const VkPipelineCreateFlags flags,
const struct radv_pipeline_layout *layout);
const struct radv_pipeline_layout *layout,
unsigned subgroup_size);
void *
radv_alloc_shader_memory(struct radv_device *device,