gallium: add writable_bitmask parameter into set_shader_buffers
to indicate write usage per buffer. This is just a hint (it will be used by radeonsi). Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
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b19494c54e
commit
66a82ec6f0
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@ -536,14 +536,16 @@ dd_context_set_shader_images(struct pipe_context *_pipe,
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static void
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dd_context_set_shader_buffers(struct pipe_context *_pipe, unsigned shader,
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unsigned start, unsigned num_buffers,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct dd_context *dctx = dd_context(_pipe);
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struct pipe_context *pipe = dctx->pipe;
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safe_memcpy(&dctx->draw_state.shader_buffers[shader][start], buffers,
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sizeof(buffers[0]) * num_buffers);
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pipe->set_shader_buffers(pipe, shader, start, num_buffers, buffers);
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pipe->set_shader_buffers(pipe, shader, start, num_buffers, buffers,
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writable_bitmask);
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}
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static void
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@ -1692,7 +1692,8 @@ trace_context_set_tess_state(struct pipe_context *_context,
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static void trace_context_set_shader_buffers(struct pipe_context *_context,
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enum pipe_shader_type shader,
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unsigned start, unsigned nr,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct trace_context *tr_context = trace_context(_context);
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struct pipe_context *context = tr_context->pipe;
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@ -1703,10 +1704,12 @@ static void trace_context_set_shader_buffers(struct pipe_context *_context,
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trace_dump_arg(uint, start);
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trace_dump_arg_begin("buffers");
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trace_dump_struct_array(shader_buffer, buffers, nr);
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trace_dump_arg(uint, writable_bitmask);
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trace_dump_arg_end();
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trace_dump_call_end();
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context->set_shader_buffers(context, shader, start, nr, buffers);
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context->set_shader_buffers(context, shader, start, nr, buffers,
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writable_bitmask);
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}
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static void trace_context_set_shader_images(struct pipe_context *_context,
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@ -890,6 +890,7 @@ tc_set_shader_images(struct pipe_context *_pipe,
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struct tc_shader_buffers {
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ubyte shader, start, count;
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bool unbind;
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unsigned writable_bitmask;
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struct pipe_shader_buffer slot[0]; /* more will be allocated if needed */
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};
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@ -900,11 +901,12 @@ tc_call_set_shader_buffers(struct pipe_context *pipe, union tc_payload *payload)
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unsigned count = p->count;
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if (p->unbind) {
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pipe->set_shader_buffers(pipe, p->shader, p->start, p->count, NULL);
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pipe->set_shader_buffers(pipe, p->shader, p->start, p->count, NULL, 0);
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return;
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}
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pipe->set_shader_buffers(pipe, p->shader, p->start, p->count, p->slot);
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pipe->set_shader_buffers(pipe, p->shader, p->start, p->count, p->slot,
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p->writable_bitmask);
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for (unsigned i = 0; i < count; i++)
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pipe_resource_reference(&p->slot[i].buffer, NULL);
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@ -914,7 +916,8 @@ static void
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tc_set_shader_buffers(struct pipe_context *_pipe,
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enum pipe_shader_type shader,
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unsigned start, unsigned count,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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if (!count)
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return;
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@ -928,6 +931,7 @@ tc_set_shader_buffers(struct pipe_context *_pipe,
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p->start = start;
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p->count = count;
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p->unbind = buffers == NULL;
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p->writable_bitmask = writable_bitmask;
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if (buffers) {
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for (unsigned i = 0; i < count; i++) {
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@ -113,7 +113,8 @@ static void
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fd_set_shader_buffers(struct pipe_context *pctx,
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enum pipe_shader_type shader,
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unsigned start, unsigned count,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct fd_context *ctx = fd_context(pctx);
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struct fd_shaderbuf_stateobj *so = &ctx->shaderbuf[shader];
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@ -2561,7 +2561,8 @@ static void
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iris_set_shader_buffers(struct pipe_context *ctx,
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enum pipe_shader_type p_stage,
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unsigned start_slot, unsigned count,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct iris_context *ice = (struct iris_context *) ctx;
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struct iris_screen *screen = (struct iris_screen *)ctx->screen;
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@ -1326,7 +1326,8 @@ static void
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nvc0_set_shader_buffers(struct pipe_context *pipe,
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enum pipe_shader_type shader,
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unsigned start, unsigned nr,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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const unsigned s = nvc0_shader_stage(shader);
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if (!nvc0_bind_buffers_range(nvc0_context(pipe), s, start, nr, buffers))
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@ -4043,7 +4043,8 @@ static void evergreen_set_hw_atomic_buffers(struct pipe_context *ctx,
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static void evergreen_set_shader_buffers(struct pipe_context *ctx,
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enum pipe_shader_type shader, unsigned start_slot,
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unsigned count,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct r600_context *rctx = (struct r600_context *)ctx;
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struct r600_image_state *istate = NULL;
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@ -1594,7 +1594,7 @@ static void r600_restore_qbo_state(struct r600_common_context *rctx,
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rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
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pipe_resource_reference(&st->saved_const0.buffer, NULL);
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rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
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rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo, ~0);
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for (unsigned i = 0; i < 3; ++i)
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pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
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}
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@ -1728,7 +1728,7 @@ static void r600_query_hw_get_result_resource(struct r600_common_context *rctx,
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rctx->b.set_constant_buffer(&rctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
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rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
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rctx->b.set_shader_buffers(&rctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo, ~0);
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if (wait && qbuf == &query->buffer) {
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uint64_t va;
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@ -135,7 +135,7 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
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sb[1].buffer_offset = src_offset;
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sb[1].buffer_size = size;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 2, sb);
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 2, sb, 0x1);
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if (!sctx->cs_copy_buffer) {
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sctx->cs_copy_buffer = si_create_dma_compute_shader(&sctx->b,
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@ -151,7 +151,7 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
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for (unsigned i = 0; i < 4; i++)
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sctx->cs_user_data[i] = clear_value[i % (clear_value_size / 4)];
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, sb);
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, 1, sb, 0x1);
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if (!sctx->cs_clear_buffer) {
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sctx->cs_clear_buffer = si_create_dma_compute_shader(&sctx->b,
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@ -172,7 +172,7 @@ static void si_compute_do_clear_or_copy(struct si_context *sctx,
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/* Restore states. */
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ctx->bind_compute_state(ctx, saved_cs);
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb);
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, src ? 2 : 1, saved_sb, ~0);
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si_compute_internal_end(sctx);
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}
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@ -1353,7 +1353,8 @@ static void si_set_shader_buffer(struct si_context *sctx,
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static void si_set_shader_buffers(struct pipe_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_shader_buffer *sbuffers)
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const struct pipe_shader_buffer *sbuffers,
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unsigned writable_bitmask)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->const_and_shader_buffers[shader];
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@ -1439,7 +1439,7 @@ static void si_restore_qbo_state(struct si_context *sctx,
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sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
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pipe_resource_reference(&st->saved_const0.buffer, NULL);
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sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
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sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo, ~0);
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for (unsigned i = 0; i < 3; ++i)
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pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
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}
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@ -1570,7 +1570,8 @@ static void si_query_hw_get_result_resource(struct si_context *sctx,
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si_resource(resource)->TC_L2_dirty = true;
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}
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sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo);
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sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo,
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1 << 2);
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if (wait && qbuf == &query->buffer) {
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uint64_t va;
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@ -233,7 +233,8 @@ void si_test_dma_perf(struct si_screen *sscreen)
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sctx->flags |= SI_CONTEXT_INV_VMEM_L1 |
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SI_CONTEXT_INV_SMEM_L1;
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0, is_copy ? 2 : 1, sb);
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ctx->set_shader_buffers(ctx, PIPE_SHADER_COMPUTE, 0,
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is_copy ? 2 : 1, sb, 0x1);
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ctx->bind_compute_state(ctx, cs);
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sctx->cs_max_waves_per_sh = cs_waves_per_sh;
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@ -56,7 +56,8 @@ static void softpipe_set_shader_buffers(struct pipe_context *pipe,
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enum pipe_shader_type shader,
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unsigned start,
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unsigned num,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct softpipe_context *softpipe = softpipe_context(pipe);
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unsigned i;
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@ -583,7 +583,8 @@ tegra_set_debug_callback(struct pipe_context *pcontext,
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static void
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tegra_set_shader_buffers(struct pipe_context *pcontext, unsigned int shader,
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unsigned start, unsigned count,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct tegra_context *context = to_tegra_context(pcontext);
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@ -1218,7 +1218,8 @@ static void
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v3d_set_shader_buffers(struct pipe_context *pctx,
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enum pipe_shader_type shader,
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unsigned start, unsigned count,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct v3d_context *v3d = v3d_context(pctx);
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struct v3d_ssbo_stateobj *so = &v3d->ssbo[shader];
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@ -1044,7 +1044,8 @@ static void virgl_set_hw_atomic_buffers(struct pipe_context *ctx,
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static void virgl_set_shader_buffers(struct pipe_context *ctx,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_shader_buffer *buffers)
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask)
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{
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struct virgl_context *vctx = virgl_context(ctx);
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struct virgl_screen *rs = virgl_screen(ctx->screen);
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@ -352,11 +352,14 @@ struct pipe_context {
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* should contain at least \a count elements
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* unless it's NULL, in which case no buffers will
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* be bound.
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* \param writable_bitmask If bit i is not set, buffers[i] will only be
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* used with loads. If unsure, set to ~0.
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*/
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void (*set_shader_buffers)(struct pipe_context *,
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enum pipe_shader_type shader,
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unsigned start_slot, unsigned count,
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const struct pipe_shader_buffer *buffers);
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const struct pipe_shader_buffer *buffers,
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unsigned writable_bitmask);
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/**
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* Bind an array of hw atomic buffers for use by all shaders.
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@ -81,7 +81,7 @@ st_bind_atomics(struct st_context *st, struct gl_program *prog,
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st_binding_to_sb(&st->ctx->AtomicBufferBindings[atomic->Binding], &sb);
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st->pipe->set_shader_buffers(st->pipe, shader_type,
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atomic->Binding, 1, &sb);
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atomic->Binding, 1, &sb, 0x1);
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}
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}
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@ -82,14 +82,14 @@ st_bind_ssbos(struct st_context *st, struct gl_program *prog,
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}
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}
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st->pipe->set_shader_buffers(st->pipe, shader_type, buffer_base,
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prog->info.num_ssbos, buffers);
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prog->info.num_ssbos, buffers, ~0);
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/* clear out any stale shader buffers */
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if (prog->info.num_ssbos < c->MaxShaderStorageBlocks)
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st->pipe->set_shader_buffers(
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st->pipe, shader_type,
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buffer_base + prog->info.num_ssbos,
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c->MaxShaderStorageBlocks - prog->info.num_ssbos,
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NULL);
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NULL, 0);
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}
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void st_bind_vs_ssbos(struct st_context *st)
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