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nvc0: fix up TCP header on GM107+ 

The number of outputs patch (limited to 255) has moved in the TCP
header, but blob seems to also set the old position. Also, the high
8-bits are now located inbetween the min/max parallel output read
address at position 20.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Samuel Pitoiset 2016-06-14 18:40:29 +02:00
parent 2060f19b4f
commit 653af07119
1 changed files with 9 additions and 0 deletions
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9
src/gallium/drivers/nouveau/nvc0/nvc0_program.c
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@ -346,6 +346,15 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
nvc0_vtgp_gen_header(tcp, info);
if (info->target >= NVISA_GM107_CHIPSET) {
/* On GM107+, the number of output patch components has moved in the TCP
* header, but it seems like blob still also uses the old position.
* Also, the high 8-bits are located inbetween the min/max parallel
* field and has to be set after updating the outputs. */
tcp->hdr[3] = (opcs & 0x0f) << 28;
tcp->hdr[4] |= (opcs & 0xf0) << 16;
}
nvc0_tp_get_tess_mode(tcp, info);
return 0;