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i965: Use brw_emit_reloc() instead of drm_bacon_bo_emit_reloc(). 

I'm about to make brw_emit_reloc do actual work, so everybody needs
to start using it and not the raw drm_bacon function.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Kenneth Graunke 2017-03-28 14:41:39 -07:00
parent eadd5d1b51
commit 6537a3ca11
11 changed files with 82 additions and 95 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/mesa/drivers/dri/i965/brw_cc.c
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@ -236,11 +236,11 @@ static void upload_cc_unit(struct brw_context *brw)
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
/* Emit CC viewport relocation */
drm_bacon_bo_emit_reloc(brw->batch.bo,
(brw->cc.state_offset +
offsetof(struct brw_cc_unit_state, cc4)),
brw->batch.bo, brw->cc.vp_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
brw_emit_reloc(&brw->batch,
(brw->cc.state_offset +
offsetof(struct brw_cc_unit_state, cc4)),
brw->batch.bo, brw->cc.vp_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
}
const struct brw_tracked_state brw_cc_unit = {

11
src/mesa/drivers/dri/i965/brw_clip_state.c
View File

@ -29,6 +29,7 @@
* Keith Whitwell <keithw@vmware.com>
*/
#include "intel_batchbuffer.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
@ -136,11 +137,11 @@ brw_upload_clip_unit(struct brw_context *brw)
(brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5;
/* emit clip viewport relocation */
drm_bacon_bo_emit_reloc(brw->batch.bo,
(brw->clip.state_offset +
offsetof(struct brw_clip_unit_state, clip6)),
brw->batch.bo, brw->clip.vp_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
brw_emit_reloc(&brw->batch,
(brw->clip.state_offset +
offsetof(struct brw_clip_unit_state, clip6)),
brw->batch.bo, brw->clip.vp_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
}
/* _NEW_TRANSFORM */

18
src/mesa/drivers/dri/i965/brw_context.h
View File

@ -1609,24 +1609,6 @@ brw_program_const(const struct gl_program *p)
return (const struct brw_program *) p;
}
static inline uint32_t
brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
uint32_t prog_offset)
{
if (brw->gen >= 5) {
/* Using state base address. */
return prog_offset;
}
drm_bacon_bo_emit_reloc(brw->batch.bo,
state_offset,
brw->cache.bo,
prog_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
return brw->cache.bo->offset64 + prog_offset;
}
static inline bool
brw_depth_writes_enabled(const struct brw_context *brw)
{

1
src/mesa/drivers/dri/i965/brw_gs_state.c
View File

@ -34,6 +34,7 @@
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
#include "intel_batchbuffer.h"
static void
brw_upload_gs_unit(struct brw_context *brw)

7
src/mesa/drivers/dri/i965/brw_sampler_state.c
View File

@ -104,10 +104,9 @@ brw_emit_sampler_state(struct brw_context *brw,
ss[2] = border_color_offset;
if (brw->gen < 6) {
ss[2] += brw->batch.bo->offset64; /* reloc */
drm_bacon_bo_emit_reloc(brw->batch.bo,
batch_offset_for_sampler_state + 8,
brw->batch.bo, border_color_offset,
I915_GEM_DOMAIN_SAMPLER, 0);
brw_emit_reloc(&brw->batch, batch_offset_for_sampler_state + 8,
brw->batch.bo, border_color_offset,
I915_GEM_DOMAIN_SAMPLER, 0);
}
ss[3] = SET_FIELD(max_anisotropy, BRW_SAMPLER_MAX_ANISOTROPY) |

15
src/mesa/drivers/dri/i965/brw_sf_state.c
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@ -35,6 +35,7 @@
#include "main/macros.h"
#include "main/fbobject.h"
#include "main/viewport.h"
#include "intel_batchbuffer.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
@ -133,7 +134,6 @@ static void upload_sf_unit( struct brw_context *brw )
{
struct gl_context *ctx = &brw->ctx;
struct brw_sf_unit_state *sf;
drm_bacon_bo *bo = brw->batch.bo;
int chipset_max_threads;
bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
@ -291,12 +291,13 @@ static void upload_sf_unit( struct brw_context *brw )
*/
/* Emit SF viewport relocation */
drm_bacon_bo_emit_reloc(bo, (brw->sf.state_offset +
offsetof(struct brw_sf_unit_state, sf5)),
brw->batch.bo, (brw->sf.vp_offset |
sf->sf5.front_winding |
(sf->sf5.viewport_transform << 1)),
I915_GEM_DOMAIN_INSTRUCTION, 0);
brw_emit_reloc(&brw->batch,
brw->sf.state_offset +
offsetof(struct brw_sf_unit_state, sf5),
brw->batch.bo,
brw->sf.vp_offset | sf->sf5.front_winding |
(sf->sf5.viewport_transform << 1),
I915_GEM_DOMAIN_INSTRUCTION, 0);
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;
}

26
src/mesa/drivers/dri/i965/brw_vs_state.c
View File

@ -31,6 +31,7 @@
#include "intel_batchbuffer.h"
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
@ -159,23 +160,22 @@ brw_upload_vs_unit(struct brw_context *brw)
/* BRW_NEW_SAMPLER_STATE_TABLE - reloc */
vs->vs5.sampler_state_pointer =
(brw->batch.bo->offset64 + stage_state->sampler_offset) >> 5;
drm_bacon_bo_emit_reloc(brw->batch.bo,
stage_state->state_offset +
offsetof(struct brw_vs_unit_state, vs5),
brw->batch.bo,
(stage_state->sampler_offset |
vs->vs5.sampler_count),
I915_GEM_DOMAIN_INSTRUCTION, 0);
brw_emit_reloc(&brw->batch,
stage_state->state_offset +
offsetof(struct brw_vs_unit_state, vs5),
brw->batch.bo,
(stage_state->sampler_offset | vs->vs5.sampler_count),
I915_GEM_DOMAIN_INSTRUCTION, 0);
}
/* Emit scratch space relocation */
if (prog_data->total_scratch != 0) {
drm_bacon_bo_emit_reloc(brw->batch.bo,
stage_state->state_offset +
offsetof(struct brw_vs_unit_state, thread2),
stage_state->scratch_bo,
vs->thread2.per_thread_scratch_space,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
brw_emit_reloc(&brw->batch,
stage_state->state_offset +
offsetof(struct brw_vs_unit_state, thread2),
stage_state->scratch_bo,
vs->thread2.per_thread_scratch_space,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;

26
src/mesa/drivers/dri/i965/brw_wm_state.c
View File

@ -222,23 +222,23 @@ brw_upload_wm_unit(struct brw_context *brw)
/* Emit scratch space relocation */
if (prog_data->base.total_scratch != 0) {
drm_bacon_bo_emit_reloc(brw->batch.bo,
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, thread2),
brw->wm.base.scratch_bo,
wm->thread2.per_thread_scratch_space,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
brw_emit_reloc(&brw->batch,
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, thread2),
brw->wm.base.scratch_bo,
wm->thread2.per_thread_scratch_space,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
/* Emit sampler state relocation */
if (brw->wm.base.sampler_count != 0) {
drm_bacon_bo_emit_reloc(brw->batch.bo,
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, wm4),
brw->batch.bo, (brw->wm.base.sampler_offset |
wm->wm4.stats_enable |
(wm->wm4.sampler_count << 2)),
I915_GEM_DOMAIN_INSTRUCTION, 0);
brw_emit_reloc(&brw->batch,
brw->wm.base.state_offset +
offsetof(struct brw_wm_unit_state, wm4),
brw->batch.bo,
brw->wm.base.sampler_offset | wm->wm4.stats_enable |
(wm->wm4.sampler_count << 2),
I915_GEM_DOMAIN_INSTRUCTION, 0);
}
brw->ctx.NewDriverState |= BRW_NEW_GEN4_UNIT_STATE;

43
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
View File

@ -168,10 +168,8 @@ brw_emit_surface_state(struct brw_context *brw,
.mocs = mocs, .clear_color = clear_color,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
drm_bacon_bo_emit_reloc(brw->batch.bo,
*surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset,
read_domains, write_domains);
brw_emit_reloc(&brw->batch, *surf_offset + brw->isl_dev.ss.addr_offset,
mt->bo, offset, read_domains, write_domains);
if (aux_surf) {
/* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
@ -182,10 +180,10 @@ brw_emit_surface_state(struct brw_context *brw,
*/
assert((aux_offset & 0xfff) == 0);
uint32_t *aux_addr = state + brw->isl_dev.ss.aux_addr_offset;
drm_bacon_bo_emit_reloc(brw->batch.bo,
*surf_offset + brw->isl_dev.ss.aux_addr_offset,
aux_bo, *aux_addr - aux_bo->offset64,
read_domains, write_domains);
brw_emit_reloc(&brw->batch,
*surf_offset + brw->isl_dev.ss.aux_addr_offset,
aux_bo, *aux_addr - aux_bo->offset64,
read_domains, write_domains);
}
}
@ -667,11 +665,10 @@ brw_emit_buffer_surface_state(struct brw_context *brw,
.mocs = tex_mocs[brw->gen]);
if (bo) {
drm_bacon_bo_emit_reloc(brw->batch.bo,
*out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
brw_emit_reloc(&brw->batch, *out_offset + brw->isl_dev.ss.addr_offset,
bo, buffer_offset,
I915_GEM_DOMAIN_SAMPLER,
(rw ? I915_GEM_DOMAIN_SAMPLER : 0));
}
}
@ -842,10 +839,8 @@ brw_update_sol_surface(struct brw_context *brw,
surf[5] = 0;
/* Emit relocation to surface contents. */
drm_bacon_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
bo, offset_bytes,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
brw_emit_reloc(&brw->batch, *out_offset + 4, bo, offset_bytes,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
/* Creates a new WM constant buffer reflecting the current fragment program's
@ -968,10 +963,8 @@ brw_emit_null_surface_state(struct brw_context *brw,
surf[5] = 0;
if (bo) {
drm_bacon_bo_emit_reloc(brw->batch.bo,
*out_offset + 4,
bo, 0,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
brw_emit_reloc(&brw->batch, *out_offset + 4, bo, 0,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
}
}
@ -1071,12 +1064,8 @@ gen4_update_renderbuffer_surface(struct brw_context *brw,
}
}
drm_bacon_bo_emit_reloc(brw->batch.bo,
offset + 4,
mt->bo,
surf[1] - mt->bo->offset64,
I915_GEM_DOMAIN_RENDER,
I915_GEM_DOMAIN_RENDER);
brw_emit_reloc(&brw->batch, offset + 4, mt->bo, surf[1] - mt->bo->offset64,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
return offset;
}

5
src/mesa/drivers/dri/i965/genX_blorp_exec.c
View File

@ -69,9 +69,8 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
struct brw_context *brw = batch->driver_batch;
drm_bacon_bo *bo = address.buffer;
drm_bacon_bo_emit_reloc(brw->batch.bo, ss_offset,
bo, address.offset + delta,
address.read_domains, address.write_domain);
brw_emit_reloc(&brw->batch, ss_offset, bo, address.offset + delta,
address.read_domains, address.write_domain);
uint64_t reloc_val = bo->offset64 + address.offset + delta;
void *reloc_ptr = (void *)brw->batch.map + ss_offset;

15
src/mesa/drivers/dri/i965/intel_batchbuffer.h
View File

@ -69,6 +69,21 @@ uint64_t brw_emit_reloc(struct intel_batchbuffer *batch, uint32_t batch_offset,
drm_bacon_bo *target, uint32_t target_offset,
uint32_t read_domains, uint32_t write_domain);
static inline uint32_t
brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
uint32_t prog_offset)
{
if (brw->gen >= 5) {
/* Using state base address. */
return prog_offset;
}
brw_emit_reloc(&brw->batch, state_offset, brw->cache.bo, prog_offset,
I915_GEM_DOMAIN_INSTRUCTION, 0);
return brw->cache.bo->offset64 + prog_offset;
}
#define USED_BATCH(batch) ((uintptr_t)((batch).map_next - (batch).map))
static inline uint32_t float_as_int(float f)