radeonsi: move index buffer calculations in si_emit_draw_packets up
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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@ -520,6 +520,8 @@ static void si_emit_draw_packets(struct si_context *sctx,
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struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
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unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
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bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
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uint32_t index_max_size = 0;
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uint64_t index_va = 0;
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if (info->count_from_stream_output) {
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struct r600_so_target *t =
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@ -567,6 +569,16 @@ static void si_emit_draw_packets(struct si_context *sctx,
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assert(!"unreachable");
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return;
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}
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index_max_size = (ib->buffer->width0 - ib->offset) /
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ib->index_size;
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index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
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assert(index_va % 2 == 0);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource *)ib->buffer,
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RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
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}
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if (!info->indirect) {
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@ -608,16 +620,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
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}
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if (info->indexed) {
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uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
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ib->index_size;
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uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource *)ib->buffer,
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RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
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if (info->indirect) {
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assert(index_va % 2 == 0);
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assert(info->indirect_offset % 4 == 0);
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radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
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