i965/vec4: Implement VS_OPCODE_GET_BUFFER_SIZE
Notice that Skylake needs to include a header in the sampler message so it will need some tweaks to work there. Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
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@ -1084,6 +1084,9 @@ enum opcode {
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VS_OPCODE_PULL_CONSTANT_LOAD,
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VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
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VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,
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VS_OPCODE_GET_BUFFER_SIZE,
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VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
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/**
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@ -745,6 +745,9 @@ brw_instruction_name(enum opcode op)
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case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
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return "set_simd4x2_header_gen9";
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case VS_OPCODE_GET_BUFFER_SIZE:
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return "vs_get_buffer_size";
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case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
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return "unpack_flags_simd4x2";
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@ -332,6 +332,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
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case SHADER_OPCODE_TG4:
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case SHADER_OPCODE_TG4_OFFSET:
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case SHADER_OPCODE_SAMPLEINFO:
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case VS_OPCODE_GET_BUFFER_SIZE:
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return inst->header_size;
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default:
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unreachable("not reached");
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@ -560,6 +560,12 @@ private:
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struct brw_reg offset);
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void generate_set_simd4x2_header_gen9(vec4_instruction *inst,
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struct brw_reg dst);
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void generate_get_buffer_size(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src,
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struct brw_reg index);
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void generate_unpack_flags(struct brw_reg dst);
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const struct brw_compiler *compiler;
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@ -1032,6 +1032,32 @@ vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
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brw_mark_surface_used(&prog_data->base, surf_index);
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}
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void
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vec4_generator::generate_get_buffer_size(vec4_instruction *inst,
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struct brw_reg dst,
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struct brw_reg src,
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struct brw_reg surf_index)
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{
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assert(devinfo->gen >= 7);
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assert(surf_index.type == BRW_REGISTER_TYPE_UD &&
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surf_index.file == BRW_IMMEDIATE_VALUE);
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brw_SAMPLE(p,
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dst,
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inst->base_mrf,
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src,
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surf_index.dw1.ud,
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0,
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GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
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1, /* response length */
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inst->mlen,
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inst->header_size > 0,
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BRW_SAMPLER_SIMD_MODE_SIMD4X2,
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BRW_SAMPLER_RETURN_FORMAT_SINT32);
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brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
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}
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void
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vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
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struct brw_reg dst,
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@ -1409,6 +1435,11 @@ vec4_generator::generate_code(const cfg_t *cfg)
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generate_set_simd4x2_header_gen9(inst, dst);
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break;
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case VS_OPCODE_GET_BUFFER_SIZE:
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generate_get_buffer_size(inst, dst, src[0], src[1]);
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break;
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case GS_OPCODE_URB_WRITE:
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generate_gs_urb_write(inst);
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break;
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