r600g: add occlusion query support
Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Dave Airlie
Jerome Glisse
parent
3aaec4750d
commit
63d010115c
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@ -32,8 +32,10 @@
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#include "r600_screen.h"
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#include "r600_context.h"
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static void r600_blitter_save_states(struct r600_context *rctx)
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static void r600_blitter_save_states(struct pipe_context *ctx)
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{
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struct r600_context *rctx = r600_context(ctx);
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util_blitter_save_blend(rctx->blitter, rctx->blend);
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util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa);
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if (rctx->stencil_ref) {
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@ -47,8 +49,9 @@ static void r600_blitter_save_states(struct r600_context *rctx)
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if (rctx->viewport) {
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util_blitter_save_viewport(rctx->blitter, &rctx->viewport->state.viewport);
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}
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if (rctx->clip)
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util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
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if (rctx->clip) {
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util_blitter_save_clip(rctx->blitter, &rctx->clip->state.clip);
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}
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util_blitter_save_vertex_buffers(rctx->blitter, rctx->nvertex_buffer,
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rctx->vertex_buffer);
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@ -60,37 +63,44 @@ static void r600_blitter_save_states(struct r600_context *rctx)
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rctx->rasterizer = NULL;
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rctx->dsa = NULL;
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rctx->vertex_elements = NULL;
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/* suspend queries */
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r600_queries_suspend(ctx);
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}
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static void r600_clear(struct pipe_context *ctx, unsigned buffers,
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const float *rgba, double depth, unsigned stencil)
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const float *rgba, double depth, unsigned stencil)
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{
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struct r600_context *rctx = r600_context(ctx);
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struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
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r600_blitter_save_states(rctx);
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r600_blitter_save_states(ctx);
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util_blitter_clear(rctx->blitter, fb->width, fb->height,
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fb->nr_cbufs, buffers, rgba, depth,
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stencil);
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/* resume queries */
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r600_queries_resume(ctx);
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}
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static void r600_clear_render_target(struct pipe_context *pipe,
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static void r600_clear_render_target(struct pipe_context *ctx,
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struct pipe_surface *dst,
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const float *rgba,
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unsigned dstx, unsigned dsty,
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unsigned width, unsigned height)
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{
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struct r600_context *rctx = r600_context(pipe);
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struct r600_context *rctx = r600_context(ctx);
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struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
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r600_blitter_save_states(rctx);
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r600_blitter_save_states(ctx);
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util_blitter_save_framebuffer(rctx->blitter, fb);
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util_blitter_clear_render_target(rctx->blitter, dst, rgba,
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dstx, dsty, width, height);
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/* resume queries */
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r600_queries_resume(ctx);
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}
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static void r600_clear_depth_stencil(struct pipe_context *pipe,
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static void r600_clear_depth_stencil(struct pipe_context *ctx,
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struct pipe_surface *dst,
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unsigned clear_flags,
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double depth,
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@ -98,14 +108,16 @@ static void r600_clear_depth_stencil(struct pipe_context *pipe,
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unsigned dstx, unsigned dsty,
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unsigned width, unsigned height)
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{
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struct r600_context *rctx = r600_context(pipe);
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struct r600_context *rctx = r600_context(ctx);
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struct pipe_framebuffer_state *fb = &rctx->framebuffer->state.framebuffer;
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r600_blitter_save_states(rctx);
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r600_blitter_save_states(ctx);
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util_blitter_save_framebuffer(rctx->blitter, fb);
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util_blitter_clear_depth_stencil(rctx->blitter, dst, clear_flags, depth, stencil,
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dstx, dsty, width, height);
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/* resume queries */
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r600_queries_resume(ctx);
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}
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static void r600_resource_copy_region(struct pipe_context *pipe,
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@ -34,6 +34,7 @@
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#include "r600_resource.h"
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#include "r600d.h"
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static void r600_destroy_context(struct pipe_context *context)
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{
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struct r600_context *rctx = r600_context(context);
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@ -46,26 +47,34 @@ void r600_flush(struct pipe_context *ctx, unsigned flags,
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{
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struct r600_context *rctx = r600_context(ctx);
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struct r600_screen *rscreen = rctx->screen;
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struct r600_query *rquery;
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static int dc = 0;
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char dname[256];
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/* suspend queries */
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r600_queries_suspend(rctx);
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if (radeon_ctx_pm4(rctx->ctx))
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return;
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goto out;
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/* FIXME dumping should be removed once shader support instructions
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* without throwing bad code
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*/
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if (!rctx->ctx->cpm4)
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goto out;
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sprintf(dname, "gallium-%08d.bof", dc);
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if (dc < 1)
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if (dc < 10)
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radeon_ctx_dump_bof(rctx->ctx, dname);
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#if 1
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radeon_ctx_submit(rctx->ctx);
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#endif
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LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
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rquery->flushed = true;
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}
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dc++;
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out:
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rctx->ctx = radeon_ctx_decref(rctx->ctx);
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rctx->ctx = radeon_ctx(rscreen->rw);
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/* resume queries */
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r600_queries_resume(rctx);
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}
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static void r600_init_config(struct r600_context *rctx)
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@ -30,9 +30,32 @@
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#include <tgsi/tgsi_parse.h>
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#include <tgsi/tgsi_util.h>
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#include <util/u_blitter.h>
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#include <util/u_double_list.h>
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#include "radeon.h"
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#include "r600_shader.h"
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#define R600_QUERY_STATE_STARTED (1 << 0)
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#define R600_QUERY_STATE_ENDED (1 << 1)
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#define R600_QUERY_STATE_SUSPENDED (1 << 2)
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struct r600_query {
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u64 result;
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/* The kind of query. Currently only OQ is supported. */
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unsigned type;
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/* How many results have been written, in dwords. It's incremented
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* after end_query and flush. */
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unsigned num_results;
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/* if we've flushed the query */
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boolean flushed;
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unsigned state;
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/* The buffer where query results are stored. */
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struct radeon_bo *buffer;
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unsigned buffer_size;
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/* linked list of queries */
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struct list_head list;
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struct radeon_state *rstate;
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};
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/* XXX move this to a more appropriate place */
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union pipe_states {
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struct pipe_rasterizer_state rasterizer;
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@ -142,7 +165,8 @@ struct r600_context {
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struct r600_vertex_element *vertex_elements;
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struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
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struct pipe_index_buffer index_buffer;
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struct pipe_blend_color blend_color;
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struct pipe_blend_color blend_color;
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struct list_head query_list;
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};
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/* Convenience cast wrapper. */
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@ -151,6 +175,11 @@ static INLINE struct r600_context *r600_context(struct pipe_context *pipe)
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return (struct r600_context*)pipe;
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}
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static INLINE struct r600_query* r600_query(struct pipe_query* q)
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{
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return (struct r600_query*)q;
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}
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struct r600_context_state *r600_context_state(struct r600_context *rctx, unsigned type, const void *state);
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struct r600_context_state *r600_context_state_incref(struct r600_context_state *rstate);
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struct r600_context_state *r600_context_state_decref(struct r600_context_state *rstate);
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@ -179,4 +208,10 @@ extern int r600_pipe_shader_update(struct pipe_context *ctx,
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uint32_t r600_translate_texformat(enum pipe_format format,
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const unsigned char *swizzle_view,
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uint32_t *word4_p, uint32_t *yuv_format_p);
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/* query */
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extern void r600_queries_resume(struct pipe_context *ctx);
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extern void r600_queries_suspend(struct pipe_context *ctx);
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#endif
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@ -24,39 +24,233 @@
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* Jerome Glisse
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* Corbin Simpson
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*/
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#include <errno.h>
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#include <util/u_inlines.h>
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#include <util/u_format.h>
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#include <util/u_memory.h>
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#include "r600_screen.h"
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#include "r600_context.h"
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static struct pipe_query *r600_create_query(struct pipe_context *pipe, unsigned query_type)
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static struct radeon_state *r600_query_begin(struct r600_context *rctx, struct r600_query *rquery)
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{
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return NULL;
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struct r600_screen *rscreen = rctx->screen;
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struct radeon_state *rstate;
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rstate = radeon_state(rscreen->rw, R600_QUERY_BEGIN_TYPE, R600_QUERY_BEGIN);
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if (rstate == NULL)
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return NULL;
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rstate->states[R600_QUERY__OFFSET] = rquery->num_results;
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rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
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rstate->nbo = 1;
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rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
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if (radeon_state_pm4(rstate)) {
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radeon_state_decref(rstate);
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return NULL;
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}
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return rstate;
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}
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static void r600_destroy_query(struct pipe_context *pipe, struct pipe_query *query)
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static struct radeon_state *r600_query_end(struct r600_context *rctx, struct r600_query *rquery)
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{
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struct r600_screen *rscreen = rctx->screen;
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struct radeon_state *rstate;
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rstate = radeon_state(rscreen->rw, R600_QUERY_END_TYPE, R600_QUERY_END);
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if (rstate == NULL)
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return NULL;
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rstate->states[R600_QUERY__OFFSET] = rquery->num_results + 8;
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rstate->bo[0] = radeon_bo_incref(rscreen->rw, rquery->buffer);
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rstate->nbo = 1;
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rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
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if (radeon_state_pm4(rstate)) {
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radeon_state_decref(rstate);
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return NULL;
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}
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return rstate;
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}
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static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type)
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{
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struct r600_screen *rscreen = r600_screen(ctx->screen);
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struct r600_context *rctx = r600_context(ctx);
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struct r600_query *q;
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if (query_type != PIPE_QUERY_OCCLUSION_COUNTER)
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return NULL;
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q = CALLOC_STRUCT(r600_query);
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if (!q)
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return NULL;
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q->type = query_type;
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LIST_ADDTAIL(&q->list, &rctx->query_list);
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q->buffer_size = 4096;
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q->buffer = radeon_bo(rscreen->rw, 0, q->buffer_size, 1, NULL);
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if (!q->buffer) {
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FREE(q);
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return NULL;
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}
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return (struct pipe_query *)q;
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}
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static void r600_destroy_query(struct pipe_context *ctx,
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struct pipe_query *query)
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{
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struct r600_screen *rscreen = r600_screen(ctx->screen);
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struct r600_query *q = r600_query(query);
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radeon_bo_decref(rscreen->rw, q->buffer);
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LIST_DEL(&q->list);
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FREE(query);
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}
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static void r600_begin_query(struct pipe_context *pipe, struct pipe_query *query)
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static void r600_query_result(struct pipe_context *ctx, struct r600_query *rquery)
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{
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struct r600_screen *rscreen = r600_screen(ctx->screen);
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u64 start, end;
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u32 *results;
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int i;
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radeon_bo_wait(rscreen->rw, rquery->buffer);
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radeon_bo_map(rscreen->rw, rquery->buffer);
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results = rquery->buffer->data;
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for (i = 0; i < rquery->num_results; i += 4) {
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start = (u64)results[i] | (u64)results[i + 1] << 32;
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end = (u64)results[i + 2] | (u64)results[i + 3] << 32;
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if ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) {
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rquery->result += end - start;
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}
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}
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radeon_bo_unmap(rscreen->rw, rquery->buffer);
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rquery->num_results = 0;
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}
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static void r600_end_query(struct pipe_context *pipe, struct pipe_query *query)
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static void r600_query_resume(struct pipe_context *ctx, struct r600_query *rquery)
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{
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struct r600_context *rctx = r600_context(ctx);
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if (rquery->num_results >= ((rquery->buffer_size >> 2) - 2)) {
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/* running out of space */
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if (!rquery->flushed) {
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ctx->flush(ctx, 0, NULL);
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}
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r600_query_result(ctx, rquery);
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}
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rquery->rstate = radeon_state_decref(rquery->rstate);
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rquery->rstate = r600_query_begin(rctx, rquery);
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rquery->flushed = false;
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}
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static boolean r600_get_query_result(struct pipe_context *pipe,
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static void r600_query_suspend(struct pipe_context *ctx, struct r600_query *rquery)
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{
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struct r600_context *rctx = r600_context(ctx);
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rquery->rstate = radeon_state_decref(rquery->rstate);
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rquery->rstate = r600_query_end(rctx, rquery);
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rquery->num_results += 16;
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}
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static void r600_begin_query(struct pipe_context *ctx, struct pipe_query *query)
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{
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struct r600_context *rctx = r600_context(ctx);
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struct r600_query *rquery = r600_query(query);
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int r;
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rquery->state = R600_QUERY_STATE_STARTED;
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rquery->num_results = 0;
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rquery->flushed = false;
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r600_query_resume(ctx, rquery);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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if (r == -EBUSY) {
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/* this shouldn't happen */
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R600_ERR("had to flush while emitting end query\n");
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ctx->flush(ctx, 0, NULL);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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}
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}
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static void r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
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{
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struct r600_context *rctx = r600_context(ctx);
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struct r600_query *rquery = r600_query(query);
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int r;
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rquery->state &= ~R600_QUERY_STATE_STARTED;
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rquery->state |= R600_QUERY_STATE_ENDED;
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r600_query_suspend(ctx, rquery);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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if (r == -EBUSY) {
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/* this shouldn't happen */
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R600_ERR("had to flush while emitting end query\n");
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ctx->flush(ctx, 0, NULL);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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}
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}
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void r600_queries_suspend(struct pipe_context *ctx)
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{
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struct r600_context *rctx = r600_context(ctx);
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struct r600_query *rquery;
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int r;
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LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
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if (rquery->state & R600_QUERY_STATE_STARTED) {
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r600_query_suspend(ctx, rquery);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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if (r == -EBUSY) {
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/* this shouldn't happen */
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R600_ERR("had to flush while emitting end query\n");
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ctx->flush(ctx, 0, NULL);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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}
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}
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rquery->state |= R600_QUERY_STATE_SUSPENDED;
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}
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}
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void r600_queries_resume(struct pipe_context *ctx)
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{
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struct r600_context *rctx = r600_context(ctx);
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struct r600_query *rquery;
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int r;
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LIST_FOR_EACH_ENTRY(rquery, &rctx->query_list, list) {
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if (rquery->state & R600_QUERY_STATE_STARTED) {
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r600_query_resume(ctx, rquery);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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if (r == -EBUSY) {
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/* this shouldn't happen */
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R600_ERR("had to flush while emitting end query\n");
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ctx->flush(ctx, 0, NULL);
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r = radeon_ctx_set_query_state(rctx->ctx, rquery->rstate);
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}
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}
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rquery->state &= ~R600_QUERY_STATE_SUSPENDED;
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}
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}
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static boolean r600_get_query_result(struct pipe_context *ctx,
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struct pipe_query *query,
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boolean wait, void *result)
|
||||
boolean wait, void *vresult)
|
||||
{
|
||||
struct r600_query *rquery = r600_query(query);
|
||||
uint64_t *result = (uint64_t*)vresult;
|
||||
|
||||
if (!rquery->flushed) {
|
||||
ctx->flush(ctx, 0, NULL);
|
||||
rquery->flushed = true;
|
||||
}
|
||||
r600_query_result(ctx, rquery);
|
||||
*result = rquery->result;
|
||||
rquery->result = 0;
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
void r600_init_query_functions(struct r600_context* rctx)
|
||||
{
|
||||
LIST_INITHEAD(&rctx->query_list);
|
||||
|
||||
rctx->context.create_query = r600_create_query;
|
||||
rctx->context.destroy_query = r600_destroy_query;
|
||||
rctx->context.begin_query = r600_begin_query;
|
||||
|
|
|
|||
|
|
@ -268,7 +268,6 @@ static void r600_set_blend_color(struct pipe_context *ctx,
|
|||
static void r600_set_clip_state(struct pipe_context *ctx,
|
||||
const struct pipe_clip_state *state)
|
||||
{
|
||||
struct r600_screen *rscreen = r600_screen(ctx->screen);
|
||||
struct r600_context *rctx = r600_context(ctx);
|
||||
struct r600_context_state *rstate;
|
||||
|
||||
|
|
|
|||
|
|
@ -151,6 +151,7 @@ struct radeon_ctx *radeon_ctx(struct radeon *radeon);
|
|||
struct radeon_ctx *radeon_ctx_decref(struct radeon_ctx *ctx);
|
||||
struct radeon_ctx *radeon_ctx_incref(struct radeon_ctx *ctx);
|
||||
int radeon_ctx_set_draw(struct radeon_ctx *ctx, struct radeon_draw *draw);
|
||||
int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state);
|
||||
int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw);
|
||||
int radeon_ctx_pm4(struct radeon_ctx *ctx);
|
||||
int radeon_ctx_submit(struct radeon_ctx *ctx);
|
||||
|
|
@ -191,8 +192,8 @@ struct radeon_ctx {
|
|||
* R600/R700
|
||||
*/
|
||||
|
||||
#define R600_NSTATE 1286
|
||||
#define R600_NTYPE 33
|
||||
#define R600_NSTATE 1288
|
||||
#define R600_NTYPE 35
|
||||
|
||||
#define R600_CONFIG 0
|
||||
#define R600_CONFIG_TYPE 0
|
||||
|
|
@ -252,14 +253,18 @@ struct radeon_ctx {
|
|||
#define R600_CB6_TYPE 27
|
||||
#define R600_CB7 1276
|
||||
#define R600_CB7_TYPE 28
|
||||
#define R600_DB 1277
|
||||
#define R600_DB_TYPE 29
|
||||
#define R600_CLIP 1278
|
||||
#define R600_CLIP_TYPE 30
|
||||
#define R600_VGT 1284
|
||||
#define R600_VGT_TYPE 31
|
||||
#define R600_DRAW 1285
|
||||
#define R600_DRAW_TYPE 32
|
||||
#define R600_QUERY_BEGIN 1277
|
||||
#define R600_QUERY_BEGIN_TYPE 29
|
||||
#define R600_QUERY_END 1278
|
||||
#define R600_QUERY_END_TYPE 30
|
||||
#define R600_DB 1279
|
||||
#define R600_DB_TYPE 31
|
||||
#define R600_CLIP 1280
|
||||
#define R600_CLIP_TYPE 32
|
||||
#define R600_VGT 1286
|
||||
#define R600_VGT_TYPE 33
|
||||
#define R600_DRAW 1287
|
||||
#define R600_DRAW_TYPE 34
|
||||
|
||||
/* R600_CONFIG */
|
||||
#define R600_CONFIG__SQ_CONFIG 0
|
||||
|
|
@ -653,4 +658,9 @@ struct radeon_ctx {
|
|||
#define R600_CLIP__PA_CL_UCP_W_0 3
|
||||
#define R600_CLIP_SIZE 4
|
||||
#define R600_CLIP_PM4 128
|
||||
/* R600 QUERY BEGIN/END */
|
||||
#define R600_QUERY__OFFSET 0
|
||||
#define R600_QUERY_SIZE 1
|
||||
#define R600_QUERY_PM4 128
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -38,6 +38,8 @@ static int r600_state_pm4_shader(struct radeon_state *state);
|
|||
static int r600_state_pm4_draw(struct radeon_state *state);
|
||||
static int r600_state_pm4_config(struct radeon_state *state);
|
||||
static int r600_state_pm4_generic(struct radeon_state *state);
|
||||
static int r600_state_pm4_query_begin(struct radeon_state *state);
|
||||
static int r600_state_pm4_query_end(struct radeon_state *state);
|
||||
static int r700_state_pm4_config(struct radeon_state *state);
|
||||
static int r700_state_pm4_cb0(struct radeon_state *state);
|
||||
static int r700_state_pm4_db(struct radeon_state *state);
|
||||
|
|
@ -240,6 +242,40 @@ static int r600_state_pm4_config(struct radeon_state *state)
|
|||
return r600_state_pm4_generic(state);
|
||||
}
|
||||
|
||||
static int r600_state_pm4_query_begin(struct radeon_state *state)
|
||||
{
|
||||
int r;
|
||||
|
||||
state->cpm4 = 0;
|
||||
state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
|
||||
state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
|
||||
state->pm4[state->cpm4++] = state->states[0];
|
||||
state->pm4[state->cpm4++] = 0x0;
|
||||
state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
|
||||
r = radeon_state_reloc(state, state->cpm4, 0);
|
||||
if (r)
|
||||
return r;
|
||||
state->pm4[state->cpm4++] = state->bo[0]->handle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r600_state_pm4_query_end(struct radeon_state *state)
|
||||
{
|
||||
int r;
|
||||
|
||||
state->cpm4 = 0;
|
||||
state->pm4[state->cpm4++] = PKT3(PKT3_EVENT_WRITE, 2);
|
||||
state->pm4[state->cpm4++] = EVENT_TYPE_ZPASS_DONE;
|
||||
state->pm4[state->cpm4++] = state->states[0];
|
||||
state->pm4[state->cpm4++] = 0x0;
|
||||
state->pm4[state->cpm4++] = PKT3(PKT3_NOP, 0);
|
||||
r = radeon_state_reloc(state, state->cpm4, 0);
|
||||
if (r)
|
||||
return r;
|
||||
state->pm4[state->cpm4++] = state->bo[0]->handle;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int r700_state_pm4_config(struct radeon_state *state)
|
||||
{
|
||||
state->pm4[state->cpm4++] = PKT3(PKT3_CONTEXT_CONTROL, 1);
|
||||
|
|
|
|||
|
|
@ -479,6 +479,10 @@ static const struct radeon_register R600_DRAW_names[] = {
|
|||
{0x000287F0, 0, 0, "VGT_DRAW_INITIATOR"},
|
||||
};
|
||||
|
||||
static const struct radeon_register R600_VGT_EVENT_names[] = {
|
||||
{0x00028A90, 1, 0, "VGT_EVENT_INITIATOR"},
|
||||
};
|
||||
|
||||
static struct radeon_type R600_types[] = {
|
||||
{ 128, 0, 0x00000000, 0x00000000, 0x0000, 0, "R600_CONFIG", 41, r600_state_pm4_config, R600_CONFIG_names},
|
||||
{ 128, 1, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB_CNTL", 18, r600_state_pm4_generic, R600_CB_CNTL_names},
|
||||
|
|
@ -509,11 +513,12 @@ static struct radeon_type R600_types[] = {
|
|||
{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
|
||||
{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
|
||||
{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
|
||||
{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
|
||||
{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
|
||||
{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
|
||||
{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
|
||||
|
||||
{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
|
||||
{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
|
||||
{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r600_state_pm4_db, R600_DB_names},
|
||||
{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
|
||||
{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
|
||||
{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
|
||||
};
|
||||
|
||||
static struct radeon_type R700_types[] = {
|
||||
|
|
@ -546,10 +551,12 @@ static struct radeon_type R700_types[] = {
|
|||
{ 128, 1274, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB5", 7, r600_state_pm4_cb0, R600_CB5_names},
|
||||
{ 128, 1275, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB6", 7, r600_state_pm4_cb0, R600_CB6_names},
|
||||
{ 128, 1276, 0x00000000, 0x00000000, 0x0000, 0, "R600_CB7", 7, r600_state_pm4_cb0, R600_CB7_names},
|
||||
{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
|
||||
{ 128, 1278, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
|
||||
{ 128, 1284, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
|
||||
{ 128, 1285, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
|
||||
{ 128, 1277, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_BEGIN", 1, r600_state_pm4_query_begin, R600_VGT_EVENT_names},
|
||||
{ 128, 1278, 0x00000000, 0x00000000, 0x0000, 0, "R600_QUERY_END", 1, r600_state_pm4_query_end, R600_VGT_EVENT_names},
|
||||
{ 128, 1279, 0x00000000, 0x00000000, 0x0000, 0, "R600_DB", 6, r700_state_pm4_db, R600_DB_names},
|
||||
{ 128, 1280, 0x00028e20, 0x00028e70, 0x0010, 0, "R600_UCP", 4, r600_state_pm4_generic, R600_UCP_names},
|
||||
{ 128, 1286, 0x00000000, 0x00000000, 0x0000, 0, "R600_VGT", 11, r600_state_pm4_vgt, R600_VGT_names},
|
||||
{ 128, 1287, 0x00000000, 0x00000000, 0x0000, 0, "R600_DRAW", 4, r600_state_pm4_draw, R600_DRAW_names},
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -82,6 +82,7 @@
|
|||
#define PKT3_SET_CTL_CONST 0x6F
|
||||
#define PKT3_SURFACE_BASE_UPDATE 0x73
|
||||
|
||||
#define EVENT_TYPE_ZPASS_DONE 0x15
|
||||
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
|
||||
|
||||
#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
|
||||
|
|
|
|||
|
|
@ -224,6 +224,41 @@ static int radeon_ctx_state_schedule(struct radeon_ctx *ctx, struct radeon_state
|
|||
return 0;
|
||||
}
|
||||
|
||||
int radeon_ctx_set_query_state(struct radeon_ctx *ctx, struct radeon_state *state)
|
||||
{
|
||||
void *tmp;
|
||||
int r = 0;
|
||||
|
||||
/* !!! ONLY ACCEPT QUERY STATE HERE !!! */
|
||||
if (state->type != R600_QUERY_BEGIN_TYPE && state->type != R600_QUERY_END_TYPE) {
|
||||
return -EINVAL;
|
||||
}
|
||||
r = radeon_state_pm4(state);
|
||||
if (r)
|
||||
return r;
|
||||
if ((ctx->draw_cpm4 + state->cpm4) > RADEON_CTX_MAX_PM4) {
|
||||
/* need to flush */
|
||||
return -EBUSY;
|
||||
}
|
||||
if (state->cpm4 >= RADEON_CTX_MAX_PM4) {
|
||||
fprintf(stderr, "%s single state too big %d, max %d\n",
|
||||
__func__, state->cpm4, RADEON_CTX_MAX_PM4);
|
||||
return -EINVAL;
|
||||
}
|
||||
tmp = realloc(ctx->state, (ctx->nstate + 1) * sizeof(void*));
|
||||
if (tmp == NULL)
|
||||
return -ENOMEM;
|
||||
ctx->state = tmp;
|
||||
ctx->state[ctx->nstate++] = radeon_state_incref(state);
|
||||
/* BEGIN/END query are balanced in the same cs so account for END
|
||||
* END query when scheduling BEGIN query
|
||||
*/
|
||||
if (state->type == R600_QUERY_BEGIN_TYPE) {
|
||||
ctx->draw_cpm4 += state->cpm4 * 2;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int radeon_ctx_set_draw_new(struct radeon_ctx *ctx, struct radeon_draw *draw)
|
||||
{
|
||||
struct radeon_draw *pdraw = NULL;
|
||||
|
|
@ -366,7 +401,6 @@ printf("%d pm4\n", ctx->cpm4);
|
|||
if (bo == NULL)
|
||||
goto out_err;
|
||||
size = bof_int32(ctx->bo[i]->size);
|
||||
printf("[%d] %d bo\n", i, size);
|
||||
if (size == NULL)
|
||||
goto out_err;
|
||||
if (bof_object_set(bo, "size", size))
|
||||
|
|
|
|||
Loading…
Reference in New Issue