ac: add has_rbplus to ac_gpu_info
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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@ -454,6 +454,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
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info->family == CHIP_RENOIR ||
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info->family == CHIP_RENOIR ||
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info->chip_class >= GFX10;
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info->chip_class >= GFX10;
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info->has_rbplus = info->family == CHIP_STONEY ||
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info->chip_class >= GFX9;
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/* Get the number of good compute units. */
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/* Get the number of good compute units. */
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info->num_good_compute_units = 0;
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info->num_good_compute_units = 0;
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for (i = 0; i < info->max_se; i++)
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for (i = 0; i < info->max_se; i++)
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@ -61,6 +61,7 @@ struct radeon_info {
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bool has_clear_state;
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bool has_clear_state;
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bool has_distributed_tess;
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bool has_distributed_tess;
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bool has_dcc_constant_encode;
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bool has_dcc_constant_encode;
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bool has_rbplus; /* if RB+ registers exist */
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/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
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/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
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/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
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/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */
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@ -356,7 +356,6 @@ radv_physical_device_init(struct radv_physical_device *device,
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if (device->rad_info.family == CHIP_STONEY ||
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if (device->rad_info.family == CHIP_STONEY ||
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device->rad_info.chip_class >= GFX9) {
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device->rad_info.chip_class >= GFX9) {
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device->has_rbplus = true;
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device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
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device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
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device->rad_info.family == CHIP_VEGA12 ||
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device->rad_info.family == CHIP_VEGA12 ||
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device->rad_info.family == CHIP_RAVEN ||
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device->rad_info.family == CHIP_RAVEN ||
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@ -865,7 +865,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
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blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
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blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
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}
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}
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if (pipeline->device->physical_device->has_rbplus) {
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if (pipeline->device->physical_device->rad_info.has_rbplus) {
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/* Disable RB+ blend optimizations for dual source blending. */
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/* Disable RB+ blend optimizations for dual source blending. */
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if (blend.mrt0_is_dual_src) {
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if (blend.mrt0_is_dual_src) {
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for (i = 0; i < 8; i++) {
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for (i = 0; i < 8; i++) {
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@ -3329,7 +3329,7 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
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radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
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radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
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radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
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radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
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if (pipeline->device->physical_device->has_rbplus) {
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if (pipeline->device->physical_device->rad_info.has_rbplus) {
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radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
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radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
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radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
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radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
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@ -4054,7 +4054,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
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else
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else
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z_order = V_02880C_LATE_Z;
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z_order = V_02880C_LATE_Z;
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bool disable_rbplus = device->physical_device->has_rbplus &&
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bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
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!device->physical_device->rbplus_allowed;
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!device->physical_device->rbplus_allowed;
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/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
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/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
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@ -280,7 +280,6 @@ struct radv_physical_device {
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int master_fd;
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int master_fd;
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struct wsi_device wsi_device;
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struct wsi_device wsi_device;
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bool has_rbplus; /* if RB+ register exist */
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bool rbplus_allowed; /* if RB+ is allowed */
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bool rbplus_allowed; /* if RB+ is allowed */
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bool cpdma_prefetch_writes_memory;
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bool cpdma_prefetch_writes_memory;
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bool has_scissor_bug;
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bool has_scissor_bug;
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@ -1181,8 +1181,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
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*/
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*/
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if (sscreen->info.family == CHIP_STONEY ||
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if (sscreen->info.family == CHIP_STONEY ||
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sscreen->info.chip_class >= GFX9) {
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sscreen->info.chip_class >= GFX9) {
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sscreen->has_rbplus = true;
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sscreen->rbplus_allowed =
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sscreen->rbplus_allowed =
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!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
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!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
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(sscreen->info.family == CHIP_STONEY ||
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(sscreen->info.family == CHIP_STONEY ||
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@ -512,7 +512,6 @@ struct si_screen {
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/* Whether shaders are monolithic (1-part) or separate (3-part). */
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/* Whether shaders are monolithic (1-part) or separate (3-part). */
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bool use_monolithic_shaders;
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bool use_monolithic_shaders;
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bool record_llvm_ir;
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bool record_llvm_ir;
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bool has_rbplus; /* if RB+ registers exist */
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bool rbplus_allowed; /* if RB+ is allowed */
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bool rbplus_allowed; /* if RB+ is allowed */
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bool dcc_msaa_allowed;
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bool dcc_msaa_allowed;
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bool cpdma_prefetch_writes_memory;
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bool cpdma_prefetch_writes_memory;
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@ -1482,7 +1482,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
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if (!rs->multisample_enable)
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if (!rs->multisample_enable)
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db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
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db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
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if (sctx->screen->has_rbplus &&
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if (sctx->screen->info.has_rbplus &&
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!sctx->screen->rbplus_allowed)
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!sctx->screen->rbplus_allowed)
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db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
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db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
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