anv/pipeline: Get rid of the kernel pointer fields
Now that we have anv_shader_bin, they're completely redundant with other information we have in the pipeline. For vertex shaders, we also go through way too much work to put the offset in one or the other field and then look at which one we put it in later. Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
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0087064f26
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623e1e06d8
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@ -488,17 +488,6 @@ anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
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ralloc_free(mem_ctx);
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}
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const struct brw_vs_prog_data *vs_prog_data =
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(const struct brw_vs_prog_data *)bin->prog_data;
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if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
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pipeline->vs_simd8 = bin->kernel.offset;
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pipeline->vs_vec4 = NO_KERNEL;
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} else {
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pipeline->vs_simd8 = NO_KERNEL;
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pipeline->vs_vec4 = bin->kernel.offset;
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}
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anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
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return VK_SUCCESS;
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@ -576,8 +565,6 @@ anv_pipeline_compile_gs(struct anv_pipeline *pipeline,
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ralloc_free(mem_ctx);
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}
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pipeline->gs_kernel = bin->kernel.offset;
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anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
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return VK_SUCCESS;
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@ -700,8 +687,6 @@ anv_pipeline_compile_fs(struct anv_pipeline *pipeline,
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ralloc_free(mem_ctx);
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}
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pipeline->ps_ksp0 = bin->kernel.offset;
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anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
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return VK_SUCCESS;
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@ -773,8 +758,6 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
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ralloc_free(mem_ctx);
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}
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pipeline->cs_simd = bin->kernel.offset;
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anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
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return VK_SUCCESS;
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@ -1024,11 +1007,6 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
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*/
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memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
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pipeline->vs_simd8 = NO_KERNEL;
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pipeline->vs_vec4 = NO_KERNEL;
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pipeline->gs_kernel = NO_KERNEL;
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pipeline->ps_ksp0 = NO_KERNEL;
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pipeline->active_stages = 0;
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const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
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@ -1389,11 +1389,6 @@ struct anv_pipeline {
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VkShaderStageFlags active_stages;
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struct anv_state blend_state;
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uint32_t vs_simd8;
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uint32_t vs_vec4;
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uint32_t ps_ksp0;
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uint32_t gs_kernel;
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uint32_t cs_simd;
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uint32_t vb_used;
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uint32_t binding_stride[MAX_VBS];
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@ -106,14 +106,14 @@ genX(graphics_pipeline_create)(
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gen7_emit_vs_workaround_flush(brw);
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#endif
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if (pipeline->vs_vec4 == NO_KERNEL) {
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if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs);
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} else {
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const struct anv_shader_bin *vs_bin =
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pipeline->shaders[MESA_SHADER_VERTEX];
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
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vs.KernelStartPointer = pipeline->vs_vec4;
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vs.KernelStartPointer = vs_bin->kernel.offset;
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vs.ScratchSpaceBasePointer = (struct anv_address) {
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.bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
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@ -139,14 +139,14 @@ genX(graphics_pipeline_create)(
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const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
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if (pipeline->gs_kernel == NO_KERNEL) {
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if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
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} else {
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const struct anv_shader_bin *gs_bin =
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pipeline->shaders[MESA_SHADER_GEOMETRY];
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
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gs.KernelStartPointer = pipeline->gs_kernel;
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gs.KernelStartPointer = gs_bin->kernel.offset;
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gs.ScratchSpaceBasePointer = (struct anv_address) {
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.bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
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@ -184,7 +184,7 @@ genX(graphics_pipeline_create)(
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}
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}
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if (pipeline->ps_ksp0 == NO_KERNEL) {
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if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_WM), wm) {
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@ -205,8 +205,8 @@ genX(graphics_pipeline_create)(
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} else {
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const struct anv_shader_bin *fs_bin =
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pipeline->shaders[MESA_SHADER_FRAGMENT];
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const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
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if (wm_prog_data->urb_setup[VARYING_SLOT_BFC0] != -1 ||
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wm_prog_data->urb_setup[VARYING_SLOT_BFC1] != -1)
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anv_finishme("two-sided color needs sbe swizzling setup");
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@ -216,9 +216,10 @@ genX(graphics_pipeline_create)(
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emit_3dstate_sbe(pipeline);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
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ps.KernelStartPointer0 = pipeline->ps_ksp0;
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ps.KernelStartPointer0 = fs_bin->kernel.offset;
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ps.KernelStartPointer1 = 0;
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ps.KernelStartPointer2 = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
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ps.KernelStartPointer2 = fs_bin->kernel.offset +
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wm_prog_data->prog_offset_2;
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ps.ScratchSpaceBasePointer = (struct anv_address) {
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.bo = anv_scratch_pool_alloc(device, &device->scratch_pool,
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@ -109,11 +109,11 @@ genX(graphics_pipeline_create)(
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wm.EarlyDepthStencilControl = NORMAL;
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}
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wm.BarycentricInterpolationMode = pipeline->ps_ksp0 == NO_KERNEL ?
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0 : wm_prog_data->barycentric_interp_modes;
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wm.BarycentricInterpolationMode =
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wm_prog_data ? wm_prog_data->barycentric_interp_modes : 0;
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}
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if (pipeline->gs_kernel == NO_KERNEL) {
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if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs);
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} else {
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const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
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@ -125,7 +125,7 @@ genX(graphics_pipeline_create)(
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), gs) {
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gs.SingleProgramFlow = false;
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gs.KernelStartPointer = pipeline->gs_kernel;
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gs.KernelStartPointer = gs_bin->kernel.offset;
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gs.VectorMaskEnable = false;
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gs.SamplerCount = get_sampler_count(gs_bin);
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gs.BindingTableEntryCount = get_binding_table_entry_count(gs_bin);
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@ -177,10 +177,7 @@ genX(graphics_pipeline_create)(
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offset = 1;
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length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
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uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
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pipeline->vs_vec4;
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if (vs_start == NO_KERNEL) {
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if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_VERTEX)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
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vs.FunctionEnable = false;
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/* Even if VS is disabled, SBE still gets the amount of
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@ -193,7 +190,7 @@ genX(graphics_pipeline_create)(
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pipeline->shaders[MESA_SHADER_VERTEX];
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), vs) {
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vs.KernelStartPointer = vs_start;
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vs.KernelStartPointer = vs_bin->kernel.offset;
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vs.SingleVertexDispatch = false;
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vs.VectorMaskEnable = false;
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@ -222,7 +219,8 @@ genX(graphics_pipeline_create)(
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vs.MaximumNumberofThreads = devinfo->max_vs_threads - 1;
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vs.StatisticsEnable = false;
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vs.SIMD8DispatchEnable = pipeline->vs_simd8 != NO_KERNEL;
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vs.SIMD8DispatchEnable =
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vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
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vs.VertexCacheDisable = false;
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vs.FunctionEnable = true;
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@ -236,7 +234,7 @@ genX(graphics_pipeline_create)(
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}
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const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
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if (pipeline->ps_ksp0 == NO_KERNEL) {
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if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_EXTRA), extra) {
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extra.PixelShaderValid = false;
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@ -248,9 +246,10 @@ genX(graphics_pipeline_create)(
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emit_3dstate_sbe(pipeline);
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anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), ps) {
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ps.KernelStartPointer0 = pipeline->ps_ksp0;
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ps.KernelStartPointer0 = fs_bin->kernel.offset;
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ps.KernelStartPointer1 = 0;
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ps.KernelStartPointer2 = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2;
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ps.KernelStartPointer2 = fs_bin->kernel.offset +
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wm_prog_data->prog_offset_2;
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ps._8PixelDispatchEnable = wm_prog_data->dispatch_8;
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ps._16PixelDispatchEnable = wm_prog_data->dispatch_16;
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ps._32PixelDispatchEnable = false;
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@ -1364,10 +1364,12 @@ flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer)
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const uint32_t slm_size = encode_slm_size(GEN_GEN, prog_data->total_shared);
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const struct anv_shader_bin *cs_bin =
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pipeline->shaders[MESA_SHADER_COMPUTE];
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struct anv_state state =
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anv_state_pool_emit(&device->dynamic_state_pool,
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GENX(INTERFACE_DESCRIPTOR_DATA), 64,
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.KernelStartPointer = pipeline->cs_simd,
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.KernelStartPointer = cs_bin->kernel.offset,
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.BindingTablePointer = surfaces.offset,
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.BindingTableEntryCount = 0,
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.SamplerStatePointer = samplers.offset,
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@ -68,10 +68,6 @@ compute_pipeline_create(
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*/
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memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
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pipeline->vs_simd8 = NO_KERNEL;
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pipeline->vs_vec4 = NO_KERNEL;
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pipeline->gs_kernel = NO_KERNEL;
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pipeline->active_stages = 0;
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pipeline->needs_data_cache = false;
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@ -366,10 +366,10 @@ emit_3dstate_sbe(struct anv_pipeline *pipeline)
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const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
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const struct brw_vue_map *fs_input_map;
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if (pipeline->gs_kernel == NO_KERNEL)
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fs_input_map = &vs_prog_data->base.vue_map;
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else
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if (gs_prog_data)
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fs_input_map = &gs_prog_data->base.vue_map;
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else
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fs_input_map = &vs_prog_data->base.vue_map;
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struct GENX(3DSTATE_SBE) sbe = {
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GENX(3DSTATE_SBE_header),
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