anv/blorp: Do more flushing around HiZ clears
We make the flush after a HiZ clear unconditional and add a flush/stall before the clear as well. Cc: mesa-stable@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760 Reviewed-by: Chad Versace <chadversary@chromium.org> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
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@ -1604,6 +1604,24 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
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ISL_AUX_USAGE_NONE, &stencil);
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}
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/* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
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*
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* "The following is required when performing a depth buffer clear with
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* using the WM_STATE or 3DSTATE_WM:
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*
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* * If other rendering operations have preceded this clear, a
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* PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
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* enabled must be issued before the rectangle primitive used for
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* the depth buffer clear operation.
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* * [...]"
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*
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* Even though the PRM only says that this is required if using 3DSTATE_WM
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* and a 3DPRIMITIVE, it appears to also sometimes hang when doing a clear
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* with WM_HZ_OP.
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*/
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cmd_buffer->state.pending_pipe_bits |=
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
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blorp_hiz_clear_depth_stencil(&batch, &depth, &stencil,
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level, base_layer, layer_count,
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area.offset.x, area.offset.y,
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@ -1618,18 +1636,22 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
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/* From the SKL PRM, Depth Buffer Clear:
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*
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* Depth Buffer Clear Workaround
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* Depth buffer clear pass using any of the methods (WM_STATE, 3DSTATE_WM
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* or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL command with
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* DEPTH_STALL bit and Depth FLUSH bits “set” before starting to render.
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* DepthStall and DepthFlush are not needed between consecutive depth clear
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* passes nor is it required if the depth-clear pass was done with
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* “full_surf_clear” bit set in the 3DSTATE_WM_HZ_OP.
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* "Depth Buffer Clear Workaround
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*
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* Depth buffer clear pass using any of the methods (WM_STATE,
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* 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
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* command with DEPTH_STALL bit and Depth FLUSH bits “set” before
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* starting to render. DepthStall and DepthFlush are not needed between
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* consecutive depth clear passes nor is it required if the depth-clear
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* pass was done with “full_surf_clear” bit set in the
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* 3DSTATE_WM_HZ_OP."
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*
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* Even though the PRM provides a bunch of conditions under which this is
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* supposedly unnecessary, we choose to perform the flush unconditionally
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* just to be safe.
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*/
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if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
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cmd_buffer->state.pending_pipe_bits |=
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
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}
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cmd_buffer->state.pending_pipe_bits |=
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
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}
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void
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