intel/compiler: Expand size of the 'nr' field
Shaders containing software implementations of double-precision operations can be very large such that we have more the 2^16 virtual registers during optimization. Move the 'nr' field to the union containing the immediate storage and expand it to 32-bits. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -221,15 +221,15 @@ struct brw_reg {
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unsigned negate:1; /* source only */
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unsigned negate:1; /* source only */
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unsigned abs:1; /* source only */
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unsigned abs:1; /* source only */
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unsigned address_mode:1; /* relative addressing, hopefully! */
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unsigned address_mode:1; /* relative addressing, hopefully! */
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unsigned pad0:1;
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unsigned pad0:17;
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unsigned subnr:5; /* :1 in align16 */
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unsigned subnr:5; /* :1 in align16 */
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unsigned nr:16;
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};
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};
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uint32_t bits;
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uint32_t bits;
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};
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};
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union {
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union {
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struct {
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struct {
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unsigned nr;
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unsigned swizzle:8; /* src only, align16 only */
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unsigned swizzle:8; /* src only, align16 only */
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unsigned writemask:4; /* dest only, align16 only */
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unsigned writemask:4; /* dest only, align16 only */
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int indirect_offset:10; /* relative addressing offset */
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int indirect_offset:10; /* relative addressing offset */
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@ -251,8 +251,7 @@ struct brw_reg {
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static inline bool
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static inline bool
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brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b)
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brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b)
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{
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{
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const bool df = a->type == BRW_REGISTER_TYPE_DF && a->file == IMM;
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return a->bits == b->bits && a->u64 == b->u64;
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return a->bits == b->bits && (df ? a->u64 == b->u64 : a->ud == b->ud);
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}
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}
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static inline bool
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static inline bool
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