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intel/compiler: Expand size of the 'nr' field 

Shaders containing software implementations of double-precision
operations can be very large such that we have more the 2^16 virtual
registers during optimization.

Move the 'nr' field to the union containing the immediate storage and
expand it to 32-bits.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Matt Turner 2018-12-10 11:48:54 -08:00
parent 7e4e9da90d
commit 622d429128
1 changed files with 3 additions and 4 deletions
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7
src/intel/compiler/brw_reg.h
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@ -221,15 +221,15 @@ struct brw_reg {
unsigned negate:1; /* source only */
unsigned abs:1; /* source only */
unsigned address_mode:1; /* relative addressing, hopefully! */
unsigned pad0:1;
unsigned pad0:17;
unsigned subnr:5; /* :1 in align16 */
unsigned nr:16;
};
uint32_t bits;
};
union {
struct {
unsigned nr;
unsigned swizzle:8; /* src only, align16 only */
unsigned writemask:4; /* dest only, align16 only */
int indirect_offset:10; /* relative addressing offset */
@ -251,8 +251,7 @@ struct brw_reg {
static inline bool
brw_regs_equal(const struct brw_reg *a, const struct brw_reg *b)
{
const bool df = a->type == BRW_REGISTER_TYPE_DF && a->file == IMM;
return a->bits == b->bits && (df ? a->u64 == b->u64 : a->ud == b->ud);
return a->bits == b->bits && a->u64 == b->u64;
}
static inline bool