radeonsi: move index buffer flushing into a non-upload indexed case
The other codepaths don't need this. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -1086,16 +1086,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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return;
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/* info->start will be added by the drawing code */
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ib.offset -= start_offset;
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} else if (sctx->b.chip_class <= CIK &&
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r600_resource(ib.buffer)->TC_L2_dirty) {
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/* VI reads index buffers through TC L2, so it doesn't
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* need this. */
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sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
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r600_resource(ib.buffer)->TC_L2_dirty = false;
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}
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}
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/* VI reads index buffers through TC L2. */
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if (info->indexed && sctx->b.chip_class <= CIK &&
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r600_resource(ib.buffer)->TC_L2_dirty) {
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sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
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r600_resource(ib.buffer)->TC_L2_dirty = false;
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}
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if (info->indirect) {
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/* Add the buffer size for memory checking in need_cs_space. */
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r600_context_add_resource_size(ctx, info->indirect);
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