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ac/surface: don't set DCC_PIPE_ALIGN modifier bit for gfx10 with 1 RB 

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
This commit is contained in:
Marek Olšák 2021-05-17 10:17:52 -04:00
parent 2acd34f266
commit 61a845ca19
1 changed files with 0 additions and 1 deletions
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1
src/amd/common/ac_surface.c
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@ -300,7 +300,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
if (info->max_render_backends == 1) {
ADD_MOD(AMD_FMT_MOD | common_dcc |
AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1) |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) |
AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B))