intel/eu/gen12: Add auxiliary type to represent SWSB information during codegen.
v2: Introduce extra tgl_swsb_sbid() constructor (Caio). Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
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@ -32,6 +32,7 @@
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#ifndef BRW_EU_DEFINES_H
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#define BRW_EU_DEFINES_H
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#include <stdint.h>
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#include "util/macros.h"
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/* The following hunk, up-to "Execution Unit" is used by both the
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@ -1004,6 +1005,153 @@ enum PACKED brw_width {
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BRW_WIDTH_16 = 4,
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};
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/**
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* Gen12+ SWSB SBID synchronization mode.
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*
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* This is represented as a bitmask including any required SBID token
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* synchronization modes, used to synchronize out-of-order instructions. Only
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* the strongest mode of the mask will be provided to the hardware in the SWSB
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* field of an actual hardware instruction, but virtual instructions may be
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* able to take into account multiple of them.
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*/
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enum tgl_sbid_mode {
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TGL_SBID_NULL = 0,
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TGL_SBID_SRC = 1,
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TGL_SBID_DST = 2,
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TGL_SBID_SET = 4
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};
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#ifdef __cplusplus
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/**
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* Allow bitwise arithmetic of tgl_sbid_mode enums.
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*/
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inline tgl_sbid_mode
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operator|(tgl_sbid_mode x, tgl_sbid_mode y)
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{
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return tgl_sbid_mode(unsigned(x) | unsigned(y));
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}
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inline tgl_sbid_mode
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operator&(tgl_sbid_mode x, tgl_sbid_mode y)
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{
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return tgl_sbid_mode(unsigned(x) & unsigned(y));
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}
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inline tgl_sbid_mode &
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operator|=(tgl_sbid_mode &x, tgl_sbid_mode y)
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{
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return x = x | y;
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}
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#endif
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/**
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* Logical representation of the SWSB scheduling information of a hardware
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* instruction. The binary representation is slightly more compact.
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*/
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struct tgl_swsb {
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unsigned regdist : 3;
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unsigned sbid : 4;
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enum tgl_sbid_mode mode : 3;
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};
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/**
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* Construct a scheduling annotation with a single RegDist dependency. This
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* synchronizes with the completion of the d-th previous in-order instruction.
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* The index is one-based, zero causes a no-op tgl_swsb to be constructed.
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*/
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static inline struct tgl_swsb
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tgl_swsb_regdist(unsigned d)
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{
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const struct tgl_swsb swsb = { d };
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assert(swsb.regdist == d);
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return swsb;
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}
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/**
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* Construct a scheduling annotation that synchronizes with the specified SBID
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* token.
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*/
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static inline struct tgl_swsb
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tgl_swsb_sbid(enum tgl_sbid_mode mode, unsigned sbid)
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{
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const struct tgl_swsb swsb = { 0, sbid, mode };
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assert(swsb.sbid == sbid);
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return swsb;
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}
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/**
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* Construct a no-op scheduling annotation.
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*/
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static inline struct tgl_swsb
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tgl_swsb_null(void)
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{
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return tgl_swsb_regdist(0);
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}
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/**
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* Return a scheduling annotation that allocates the same SBID synchronization
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* token as \p swsb. In addition it will synchronize against a previous
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* in-order instruction if \p regdist is non-zero.
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*/
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static inline struct tgl_swsb
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tgl_swsb_dst_dep(struct tgl_swsb swsb, unsigned regdist)
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{
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swsb.regdist = regdist;
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swsb.mode = swsb.mode & TGL_SBID_SET;
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return swsb;
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}
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/**
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* Return a scheduling annotation that synchronizes against the same SBID and
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* RegDist dependencies as \p swsb, but doesn't allocate any SBID token.
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*/
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static inline struct tgl_swsb
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tgl_swsb_src_dep(struct tgl_swsb swsb)
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{
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swsb.mode = swsb.mode & (TGL_SBID_SRC | TGL_SBID_DST);
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return swsb;
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}
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/**
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* Convert the provided tgl_swsb to the hardware's binary representation of an
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* SWSB annotation.
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*/
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static inline uint8_t
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tgl_swsb_encode(struct tgl_swsb swsb)
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{
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if (!swsb.mode) {
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return swsb.regdist;
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} else if (swsb.regdist) {
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return 0x80 | swsb.regdist << 4 | swsb.sbid;
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} else {
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return swsb.sbid | (swsb.mode & TGL_SBID_SET ? 0x40 :
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swsb.mode & TGL_SBID_DST ? 0x20 : 0x30);
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}
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}
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/**
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* Convert the provided binary representation of an SWSB annotation to a
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* tgl_swsb.
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*/
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static inline struct tgl_swsb
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tgl_swsb_decode(uint8_t x)
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{
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if (x & 0x80) {
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const struct tgl_swsb swsb = { (x & 0x70u) >> 4, x & 0xfu,
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TGL_SBID_DST | TGL_SBID_SET };
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return swsb;
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} else if ((x & 0x70) == 0x20) {
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return tgl_swsb_sbid(TGL_SBID_DST, x & 0xfu);
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} else if ((x & 0x70) == 0x30) {
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return tgl_swsb_sbid(TGL_SBID_SRC, x & 0xfu);
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} else if ((x & 0x70) == 0x40) {
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return tgl_swsb_sbid(TGL_SBID_SET, x & 0xfu);
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} else {
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return tgl_swsb_regdist(x & 0x7u);
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}
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}
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enum tgl_sync_function {
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TGL_SYNC_NOP = 0x0,
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TGL_SYNC_ALLRD = 0x2,
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