From 6082515de7c7b4885bd685d88aee32fc9e5103a1 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Sat, 27 Jun 2015 09:58:28 -0400 Subject: [PATCH] gallium/ttn: partial fix for output arrays It isn't quite yet practical to enable TGSI_ANY_INOUT_DECL_RANGE shader cap yet, at least not in drivers that need lower_to_scalar pass (which right now is all of the ttn users), since the register arrays do not get converted to SSA, which angers nir_lower_alu_to_scalar. Signed-off-by: Rob Clark Reviewed-by: Eric Anholt --- src/gallium/auxiliary/nir/tgsi_to_nir.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c index 065bbf050c2..c5b65eeae0c 100644 --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c @@ -1716,9 +1716,11 @@ ttn_add_output_stores(struct ttn_compile *c) for (i = 0; i < array_len; i++) { nir_intrinsic_instr *store = nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_output); + unsigned loc = var->data.driver_location + i; store->num_components = 4; - store->const_index[0] = var->data.driver_location + i; - store->src[0].reg.reg = c->output_regs[var->data.driver_location].reg; + store->const_index[0] = loc; + store->src[0].reg.reg = c->output_regs[loc].reg; + store->src[0].reg.base_offset = c->output_regs[loc].offset; nir_instr_insert_after_cf_list(b->cf_node_list, &store->instr); } }