winsys/radeon: add the implementation of fences from r300g
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48784f3591
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6067a30838
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@ -76,26 +76,19 @@ void r300_flush(struct pipe_context *pipe,
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struct pipe_fence_handle **fence)
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{
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struct r300_context *r300 = r300_context(pipe);
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struct pb_buffer **rfence = (struct pb_buffer**)fence;
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if (r300->screen->info.drm_minor >= 12) {
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flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
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}
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if (rfence) {
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/* Create a fence, which is a dummy BO. */
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*rfence = r300->rws->buffer_create(r300->rws, 1, 1, TRUE,
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RADEON_DOMAIN_GTT);
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/* Add the fence as a dummy relocation. */
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r300->rws->cs_add_reloc(r300->cs,
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r300->rws->buffer_get_cs_handle(*rfence),
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RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT);
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if (fence) {
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*fence = r300->rws->cs_create_fence(r300->cs);
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}
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if (r300->dirty_hw) {
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r300_flush_and_cleanup(r300, flags);
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} else {
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if (rfence) {
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if (fence) {
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/* We have to create a fence object, but the command stream is empty
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* and we cannot emit an empty CS. Let's write to some reg. */
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CS_LOCALS(r300);
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@ -558,17 +558,17 @@ static void r300_fence_reference(struct pipe_screen *screen,
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struct pipe_fence_handle **ptr,
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struct pipe_fence_handle *fence)
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{
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pb_reference((struct pb_buffer**)ptr,
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(struct pb_buffer*)fence);
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struct radeon_winsys *rws = r300_screen(screen)->rws;
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rws->fence_reference(ptr, fence);
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}
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static boolean r300_fence_signalled(struct pipe_screen *screen,
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struct pipe_fence_handle *fence)
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{
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struct radeon_winsys *rws = r300_screen(screen)->rws;
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struct pb_buffer *rfence = (struct pb_buffer*)fence;
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return !rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE);
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return rws->fence_wait(rws, fence, 0);
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}
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static boolean r300_fence_finish(struct pipe_screen *screen,
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@ -576,26 +576,8 @@ static boolean r300_fence_finish(struct pipe_screen *screen,
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uint64_t timeout)
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{
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struct radeon_winsys *rws = r300_screen(screen)->rws;
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struct pb_buffer *rfence = (struct pb_buffer*)fence;
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if (timeout != PIPE_TIMEOUT_INFINITE) {
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int64_t start_time = os_time_get();
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/* Convert to microseconds. */
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timeout /= 1000;
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/* Wait in a loop. */
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while (rws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) {
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if (os_time_get() - start_time >= timeout) {
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return FALSE;
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}
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os_time_sleep(10);
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}
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return TRUE;
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}
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rws->buffer_wait(rfence, RADEON_USAGE_READWRITE);
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return TRUE;
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return rws->fence_wait(rws, fence, timeout);
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}
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struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
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@ -65,6 +65,7 @@
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#include "radeon_drm_cs.h"
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#include "util/u_memory.h"
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#include "os/os_time.h"
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#include <stdio.h>
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#include <stdlib.h>
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@ -630,6 +631,58 @@ static boolean radeon_bo_is_referenced(struct radeon_winsys_cs *rcs,
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return FALSE;
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}
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/* FENCES */
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static struct pipe_fence_handle *
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radeon_cs_create_fence(struct radeon_winsys_cs *rcs)
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{
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struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
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struct pb_buffer *fence;
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/* Create a fence, which is a dummy BO. */
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fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1, TRUE,
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RADEON_DOMAIN_GTT);
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/* Add the fence as a dummy relocation. */
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cs->ws->base.cs_add_reloc(rcs, cs->ws->base.buffer_get_cs_handle(fence),
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RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT);
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return (struct pipe_fence_handle*)fence;
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}
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static bool radeon_fence_wait(struct radeon_winsys *ws,
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struct pipe_fence_handle *fence,
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uint64_t timeout)
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{
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struct pb_buffer *rfence = (struct pb_buffer*)fence;
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if (timeout == 0)
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return !ws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE);
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if (timeout != PIPE_TIMEOUT_INFINITE) {
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int64_t start_time = os_time_get();
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/* Convert to microseconds. */
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timeout /= 1000;
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/* Wait in a loop. */
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while (ws->buffer_is_busy(rfence, RADEON_USAGE_READWRITE)) {
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if (os_time_get() - start_time >= timeout) {
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return FALSE;
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}
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os_time_sleep(10);
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}
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return TRUE;
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}
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ws->buffer_wait(rfence, RADEON_USAGE_READWRITE);
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return TRUE;
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}
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static void radeon_fence_reference(struct pipe_fence_handle **dst,
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struct pipe_fence_handle *src)
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{
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pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src);
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}
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void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
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{
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ws->base.cs_create = radeon_drm_cs_create;
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@ -642,4 +695,7 @@ void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
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ws->base.cs_set_flush_callback = radeon_drm_cs_set_flush;
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ws->base.cs_is_buffer_referenced = radeon_bo_is_referenced;
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ws->base.cs_sync_flush = radeon_drm_cs_sync_flush;
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ws->base.cs_create_fence = radeon_cs_create_fence;
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ws->base.fence_wait = radeon_fence_wait;
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ws->base.fence_reference = radeon_fence_reference;
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}
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@ -484,6 +484,29 @@ struct radeon_winsys {
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*/
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void (*cs_sync_flush)(struct radeon_winsys_cs *cs);
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/**
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* Return a fence associated with the CS. The fence will be signalled
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* once the CS is flushed and all commands in the CS are completed
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* by the GPU.
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*/
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struct pipe_fence_handle *(*cs_create_fence)(struct radeon_winsys_cs *cs);
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/**
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* Wait for the fence and return true if the fence has been signalled.
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* The timeout of 0 will only return the status.
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* The timeout of PIPE_TIMEOUT_INFINITE will always wait until the fence
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* is signalled.
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*/
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bool (*fence_wait)(struct radeon_winsys *ws,
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struct pipe_fence_handle *fence,
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uint64_t timeout);
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/**
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* Reference counting for fences.
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*/
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void (*fence_reference)(struct pipe_fence_handle **dst,
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struct pipe_fence_handle *src);
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/**
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* Initialize surface
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*
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