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r600g: atomize viewport state 

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Marek Olšák 2012-09-10 19:28:34 +02:00
parent 63bf0f905a
commit 605fd0c14a
7 changed files with 27 additions and 39 deletions
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12
src/gallium/drivers/r600/evergreen_hw_context.c
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@ -77,12 +77,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
{R_028420_CB_BLEND_ALPHA, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
{R_0285BC_PA_CL_UCP0_X, 0, 0},
{R_0285C0_PA_CL_UCP0_Y, 0, 0},
{R_0285C4_PA_CL_UCP0_Z, 0, 0},
@ -406,12 +400,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_028418_CB_BLEND_GREEN, 0, 0},
{R_02841C_CB_BLEND_BLUE, 0, 0},
{R_028420_CB_BLEND_ALPHA, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
{R_0285BC_PA_CL_UCP0_X, 0, 0},
{R_0285C0_PA_CL_UCP0_Y, 0, 0},
{R_0285C4_PA_CL_UCP0_Z, 0, 0},

1
src/gallium/drivers/r600/evergreen_state.c
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@ -2191,6 +2191,7 @@ void evergreen_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7);
r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
rctx->context.create_blend_state = evergreen_create_blend_state;
rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;

4
src/gallium/drivers/r600/r600_blit.c
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@ -62,9 +62,7 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op
util_blitter_save_rasterizer(rctx->blitter, rctx->states[R600_PIPE_STATE_RASTERIZER]);
if (op & R600_SAVE_FRAGMENT_STATE) {
if (rctx->states[R600_PIPE_STATE_VIEWPORT]) {
util_blitter_save_viewport(rctx->blitter, &rctx->viewport);
}
util_blitter_save_viewport(rctx->blitter, &rctx->viewport.state);
util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader);
util_blitter_save_blend(rctx->blitter, rctx->states[R600_PIPE_STATE_BLEND]);
util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]);

7
src/gallium/drivers/r600/r600_hw_context.c
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@ -360,12 +360,6 @@ static const struct r600_reg r600_context_reg_list[] = {
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
{R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0},
{R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0},
{R_028444_PA_CL_VPORT_YSCALE_0, 0, 0},
{R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0},
{R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0},
{R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0},
{R_0286D4_SPI_INTERP_CONTROL_0, 0, 0},
{R_028810_PA_CL_CLIP_CNTL, 0, 0},
{R_028814_PA_SU_SC_MODE_CNTL, 0, 0},
@ -1050,6 +1044,7 @@ void r600_begin_new_cs(struct r600_context *ctx)
r600_atom_dirty(ctx, &ctx->db_misc_state.atom);
r600_atom_dirty(ctx, &ctx->sample_mask.atom);
r600_atom_dirty(ctx, &ctx->stencil_ref.atom);
r600_atom_dirty(ctx, &ctx->viewport.atom);
if (ctx->chip_class <= R700) {
r600_atom_dirty(ctx, &ctx->seamless_cube_map.atom);

11
src/gallium/drivers/r600/r600_pipe.h
View File

@ -35,7 +35,7 @@
#include "r600_resource.h"
#include "evergreen_compute.h"
#define R600_NUM_ATOMS 21
#define R600_NUM_ATOMS 22
#define R600_MAX_CONST_BUFFERS 2
#define R600_MAX_CONST_BUFFER_SIZE 4096
@ -115,12 +115,16 @@ struct r600_stencil_ref_state {
struct pipe_stencil_ref pipe_state;
};
struct r600_viewport_state {
struct r600_atom atom;
struct pipe_viewport_state state;
};
enum r600_pipe_state_id {
R600_PIPE_STATE_BLEND = 0,
R600_PIPE_STATE_BLEND_COLOR,
R600_PIPE_STATE_CLIP,
R600_PIPE_STATE_SCISSOR,
R600_PIPE_STATE_VIEWPORT,
R600_PIPE_STATE_RASTERIZER,
R600_PIPE_STATE_VGT,
R600_PIPE_STATE_FRAMEBUFFER,
@ -334,7 +338,6 @@ struct r600_context {
unsigned pa_sc_line_stipple;
unsigned pa_cl_clip_cntl;
/* for saving when using blitter */
struct pipe_viewport_state viewport;
struct pipe_clip_state clip;
struct r600_pipe_shader_selector *ps_shader;
struct r600_pipe_shader_selector *vs_shader;
@ -376,6 +379,7 @@ struct r600_context {
struct r600_seamless_cube_map seamless_cube_map;
struct r600_stencil_ref_state stencil_ref;
struct r600_sample_mask sample_mask;
struct r600_viewport_state viewport;
/* Shaders and shader resources. */
struct r600_cs_shader_state cs_shader_state;
struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES];
@ -577,6 +581,7 @@ void r600_translate_index_buffer(struct r600_context *r600,
void r600_init_common_state_functions(struct r600_context *rctx);
void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom);
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom);
void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id,
void (*emit)(struct r600_context *ctx, struct r600_atom *state),
unsigned num_dw);

1
src/gallium/drivers/r600/r600_state.c
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@ -2072,6 +2072,7 @@ void r600_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4);
r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 8);
rctx->context.create_blend_state = r600_create_blend_state;
rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;

30
src/gallium/drivers/r600/r600_state_common.c
View File

@ -648,26 +648,26 @@ static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
}
static void r600_set_viewport_state(struct pipe_context *ctx,
const struct pipe_viewport_state *state)
const struct pipe_viewport_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
if (rstate == NULL)
return;
rctx->viewport.state = *state;
r600_atom_dirty(rctx, &rctx->viewport.atom);
}
rctx->viewport = *state;
rstate->id = R600_PIPE_STATE_VIEWPORT;
r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom)
{
struct radeon_winsys_cs *cs = rctx->cs;
struct pipe_viewport_state *state = &rctx->viewport.state;
free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
r600_context_pipe_state_set(rctx, rstate);
r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE_0, 6);
r600_write_value(cs, fui(state->scale[0])); /* R_02843C_PA_CL_VPORT_XSCALE_0 */
r600_write_value(cs, fui(state->translate[0])); /* R_028440_PA_CL_VPORT_XOFFSET_0 */
r600_write_value(cs, fui(state->scale[1])); /* R_028444_PA_CL_VPORT_YSCALE_0 */
r600_write_value(cs, fui(state->translate[1])); /* R_028448_PA_CL_VPORT_YOFFSET_0 */
r600_write_value(cs, fui(state->scale[2])); /* R_02844C_PA_CL_VPORT_ZSCALE_0 */
r600_write_value(cs, fui(state->translate[2])); /* R_028450_PA_CL_VPORT_ZOFFSET_0 */
}
static void *r600_create_vertex_elements(struct pipe_context *ctx, unsigned count,