nouveau/nir: Disable bitfield ops pre-nvc0.
There's no hardware instructions for them until then. These chips don't expose the extension provinding the GLSL builtins for operations like bfrev, but NIR can recognize the construct and optimize it to bitfield_reverse, which pre-nvc0 would then fail to codegen. Prevents a regression when moving to nir-to-tgsi. Other lower_bitfield flags are set as well for when someone comes along and adds optimizations for them too. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Karol Herbst <kherbst@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>
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@ -3257,14 +3257,14 @@ nvir_nir_shader_compiler_options(int chipset)
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op.lower_sincos = false;
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op.lower_fmod = true;
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op.lower_bitfield_extract = false;
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op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHIPSET);
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op.lower_bitfield_insert = false;
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op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
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op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHIPSET);
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op.lower_bitfield_insert_to_bitfield_select = false;
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op.lower_bitfield_reverse = false;
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op.lower_bit_count = false;
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op.lower_ifind_msb = false;
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op.lower_find_lsb = false;
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op.lower_bitfield_reverse = (chipset < NVISA_GF100_CHIPSET);
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op.lower_bit_count = (chipset < NVISA_GF100_CHIPSET);
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op.lower_ifind_msb = (chipset < NVISA_GF100_CHIPSET);
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op.lower_find_lsb = (chipset < NVISA_GF100_CHIPSET);
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op.lower_uadd_carry = true; // TODO
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op.lower_usub_borrow = true; // TODO
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op.lower_mul_high = false;
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