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nouveau/nir: Disable bitfield ops pre-nvc0. 

There's no hardware instructions for them until then.  These chips don't
expose the extension provinding the GLSL builtins for operations like
bfrev, but NIR can recognize the construct and optimize it to
bitfield_reverse, which pre-nvc0 would then fail to codegen.  Prevents a
regression when moving to nir-to-tgsi.  Other lower_bitfield flags are set
as well for when someone comes along and adds optimizations for them too.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16063>
This commit is contained in:
Emma Anholt 2022-03-28 11:21:26 -07:00 committed by Marge Bot
parent adb6d7fe9a
commit 6040107dc1
1 changed files with 6 additions and 6 deletions
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12
src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
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@ -3257,14 +3257,14 @@ nvir_nir_shader_compiler_options(int chipset)
op.lower_sincos = false;
op.lower_fmod = true;
op.lower_bitfield_extract = false;
op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
op.lower_bitfield_extract_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHIPSET);
op.lower_bitfield_insert = false;
op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET);
op.lower_bitfield_insert_to_shifts = (chipset >= NVISA_GV100_CHIPSET || chipset < NVISA_GF100_CHIPSET);
op.lower_bitfield_insert_to_bitfield_select = false;
op.lower_bitfield_reverse = false;
op.lower_bit_count = false;
op.lower_ifind_msb = false;
op.lower_find_lsb = false;
op.lower_bitfield_reverse = (chipset < NVISA_GF100_CHIPSET);
op.lower_bit_count = (chipset < NVISA_GF100_CHIPSET);
op.lower_ifind_msb = (chipset < NVISA_GF100_CHIPSET);
op.lower_find_lsb = (chipset < NVISA_GF100_CHIPSET);
op.lower_uadd_carry = true; // TODO
op.lower_usub_borrow = true; // TODO
op.lower_mul_high = false;