r600: fix not-very indirect compute
We need to get the grid sizes earlier to fill in to the const buffer. Fixes: KHR-GL45.compute_shader.built-in-variables and KHR-GL45.compute_shader.dispatch-indirect Reviewed-by: Roland Scheidegger <sorland@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -571,7 +571,8 @@ static void evergreen_compute_upload_input(struct pipe_context *ctx,
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}
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static void evergreen_emit_dispatch(struct r600_context *rctx,
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const struct pipe_grid_info *info)
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const struct pipe_grid_info *info,
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uint32_t indirect_grid[3])
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{
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int i;
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struct radeon_winsys_cs *cs = rctx->b.gfx.cs;
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@ -631,15 +632,11 @@ static void evergreen_emit_dispatch(struct r600_context *rctx,
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lds_size | (num_waves << 14));
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if (info->indirect) {
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struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect;
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unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource, PIPE_TRANSFER_READ);
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if (data) {
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radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
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radeon_emit(cs, data[0]);
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radeon_emit(cs, data[1]);
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radeon_emit(cs, data[2]);
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radeon_emit(cs, indirect_grid[0]);
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radeon_emit(cs, indirect_grid[1]);
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radeon_emit(cs, indirect_grid[2]);
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radeon_emit(cs, 1);
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}
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} else {
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/* Dispatch packet */
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radeon_emit(cs, PKT3C(PKT3_DISPATCH_DIRECT, 3, 0));
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@ -703,6 +700,7 @@ static void compute_emit_cs(struct r600_context *rctx,
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struct r600_pipe_shader *current;
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struct r600_shader_atomic combined_atomics[8];
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uint8_t atomic_used_mask;
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uint32_t indirect_grid[3] = { 0, 0, 0 };
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/* make sure that the gfx ring is only one active */
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if (radeon_emitted(rctx->b.dma.cs, 0)) {
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@ -729,9 +727,17 @@ static void compute_emit_cs(struct r600_context *rctx,
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bool need_buf_const = current->shader.uses_tex_buffers ||
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current->shader.has_txq_cube_array_z_comp;
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if (info->indirect) {
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struct r600_resource *indirect_resource = (struct r600_resource *)info->indirect;
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unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource, PIPE_TRANSFER_READ);
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unsigned offset = info->indirect_offset / 4;
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indirect_grid[0] = data[offset];
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indirect_grid[1] = data[offset + 1];
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indirect_grid[2] = data[offset + 2];
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}
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for (int i = 0; i < 3; i++) {
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rctx->cs_block_grid_sizes[i] = info->block[i];
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rctx->cs_block_grid_sizes[i + 4] = info->grid[i];
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rctx->cs_block_grid_sizes[i + 4] = info->indirect ? indirect_grid[i] : info->grid[i];
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}
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rctx->cs_block_grid_sizes[3] = rctx->cs_block_grid_sizes[7] = 0;
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rctx->driver_consts[PIPE_SHADER_COMPUTE].cs_block_grid_size_dirty = true;
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@ -802,7 +808,7 @@ static void compute_emit_cs(struct r600_context *rctx,
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r600_emit_atom(rctx, &rctx->cs_shader_state.atom);
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/* Emit dispatch state and dispatch packet */
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evergreen_emit_dispatch(rctx, info);
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evergreen_emit_dispatch(rctx, info, indirect_grid);
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/* XXX evergreen_flush_emit() hardcodes the CP_COHER_SIZE to 0xffffffff
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*/
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