radeonsi: precompute IA_MULTI_VGT_PARAM values into a table
The perf difference is very small: 0.99% -> 0.40% for the time spent in si_get_ia_multi_vgt_param when si_draw_vbo is 20%. Pretty much nothing. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
parent
c78177fc64
commit
5f99c49008
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@ -234,6 +234,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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si_init_all_descriptors(sctx);
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si_init_all_descriptors(sctx);
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si_init_state_functions(sctx);
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si_init_state_functions(sctx);
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si_init_shader_functions(sctx);
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si_init_shader_functions(sctx);
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si_init_ia_multi_vgt_param_table(sctx);
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if (sctx->b.chip_class >= CIK)
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if (sctx->b.chip_class >= CIK)
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cik_init_sdma_functions(sctx);
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cik_init_sdma_functions(sctx);
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@ -204,6 +204,28 @@ struct si_shader_ctx_state {
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struct si_shader *current;
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struct si_shader *current;
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};
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};
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#define SI_NUM_VGT_PARAM_KEY_BITS 12
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#define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
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/* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
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* Some fields are set by state-change calls, most are set by draw_vbo.
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*/
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union si_vgt_param_key {
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struct {
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unsigned prim:4;
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unsigned uses_instancing:1;
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unsigned multi_instances_smaller_than_primgroup:1;
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unsigned primitive_restart:1;
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unsigned count_from_stream_output:1;
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unsigned line_stipple_enabled:1;
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unsigned uses_tess:1;
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unsigned tcs_tes_uses_prim_id:1;
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unsigned uses_gs:1;
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unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
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} u;
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uint32_t index;
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};
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struct si_context {
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struct si_context {
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struct r600_common_context b;
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struct r600_common_context b;
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struct blitter_context *blitter;
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struct blitter_context *blitter;
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@ -355,6 +377,10 @@ struct si_context {
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/* Other state */
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/* Other state */
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bool need_check_render_feedback;
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bool need_check_render_feedback;
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/* Precomputed IA_MULTI_VGT_PARAM */
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union si_vgt_param_key ia_multi_vgt_param_key;
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unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
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};
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};
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/* cik_sdma.c */
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/* cik_sdma.c */
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@ -918,6 +918,8 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
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si_update_poly_offset_state(sctx);
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si_update_poly_offset_state(sctx);
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si_mark_atom_dirty(sctx, &sctx->clip_regs);
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si_mark_atom_dirty(sctx, &sctx->clip_regs);
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sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
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rs->line_stipple_enable;
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sctx->do_update_shaders = true;
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sctx->do_update_shaders = true;
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}
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}
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@ -355,6 +355,7 @@ void si_destroy_shader_cache(struct si_screen *sscreen);
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void si_init_shader_selector_async(void *job, int thread_index);
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void si_init_shader_selector_async(void *job, int thread_index);
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/* si_state_draw.c */
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/* si_state_draw.c */
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void si_init_ia_multi_vgt_param_table(struct si_context *sctx);
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void si_emit_cache_flush(struct si_context *sctx);
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void si_emit_cache_flush(struct si_context *sctx);
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void si_ce_pre_draw_synchronization(struct si_context *sctx);
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void si_ce_pre_draw_synchronization(struct si_context *sctx);
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void si_ce_post_draw_synchronization(struct si_context *sctx);
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void si_ce_post_draw_synchronization(struct si_context *sctx);
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@ -261,13 +261,11 @@ static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
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}
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}
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}
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}
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static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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static unsigned
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const struct pipe_draw_info *info,
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si_get_init_multi_vgt_param(struct si_screen *sscreen,
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unsigned num_patches)
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union si_vgt_param_key *key)
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{
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{
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struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
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STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
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unsigned prim = info->mode;
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unsigned primgroup_size = 128; /* recommended without a GS */
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unsigned max_primgroup_in_wave = 2;
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unsigned max_primgroup_in_wave = 2;
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/* SWITCH_ON_EOP(0) is always preferable. */
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/* SWITCH_ON_EOP(0) is always preferable. */
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@ -277,35 +275,28 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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bool partial_vs_wave = false;
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bool partial_vs_wave = false;
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bool partial_es_wave = false;
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bool partial_es_wave = false;
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if (sctx->gs_shader.cso)
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if (key->u.uses_tess) {
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primgroup_size = 64; /* recommended with a GS */
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if (sctx->tes_shader.cso) {
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/* primgroup_size must be set to a multiple of NUM_PATCHES */
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primgroup_size = num_patches;
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/* SWITCH_ON_EOI must be set if PrimID is used. */
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/* SWITCH_ON_EOI must be set if PrimID is used. */
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if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
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if (key->u.tcs_tes_uses_prim_id)
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sctx->tes_shader.cso->info.uses_primid)
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ia_switch_on_eoi = true;
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ia_switch_on_eoi = true;
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/* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
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/* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
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if ((sctx->b.family == CHIP_TAHITI ||
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if ((sscreen->b.family == CHIP_TAHITI ||
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sctx->b.family == CHIP_PITCAIRN ||
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sscreen->b.family == CHIP_PITCAIRN ||
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sctx->b.family == CHIP_BONAIRE) &&
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sscreen->b.family == CHIP_BONAIRE) &&
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sctx->gs_shader.cso)
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key->u.uses_gs)
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partial_vs_wave = true;
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partial_vs_wave = true;
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/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
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/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
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if (sctx->screen->has_distributed_tess) {
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if (sscreen->has_distributed_tess) {
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if (sctx->gs_shader.cso) {
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if (key->u.uses_gs) {
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partial_es_wave = true;
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partial_es_wave = true;
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/* GPU hang workaround. */
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/* GPU hang workaround. */
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if (sctx->b.family == CHIP_TONGA ||
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if (sscreen->b.family == CHIP_TONGA ||
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sctx->b.family == CHIP_FIJI ||
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sscreen->b.family == CHIP_FIJI ||
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sctx->b.family == CHIP_POLARIS10 ||
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sscreen->b.family == CHIP_POLARIS10 ||
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sctx->b.family == CHIP_POLARIS11)
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sscreen->b.family == CHIP_POLARIS11)
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partial_vs_wave = true;
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partial_vs_wave = true;
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} else {
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} else {
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partial_vs_wave = true;
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partial_vs_wave = true;
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@ -314,13 +305,13 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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}
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}
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/* This is a hardware requirement. */
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/* This is a hardware requirement. */
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if ((rs && rs->line_stipple_enable) ||
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if (key->u.line_stipple_enabled ||
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(sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
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(sscreen->b.debug_flags & DBG_SWITCH_ON_EOP)) {
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ia_switch_on_eop = true;
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ia_switch_on_eop = true;
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wd_switch_on_eop = true;
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wd_switch_on_eop = true;
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}
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}
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if (sctx->b.chip_class >= CIK) {
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if (sscreen->b.chip_class >= CIK) {
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/* WD_SWITCH_ON_EOP has no effect on GPUs with less than
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/* WD_SWITCH_ON_EOP has no effect on GPUs with less than
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* 4 shader engines. Set 1 to pass the assertion below.
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* 4 shader engines. Set 1 to pass the assertion below.
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* The other cases are hardware requirements.
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* The other cases are hardware requirements.
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@ -328,24 +319,24 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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* Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
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* Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
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* for points, line strips, and tri strips.
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* for points, line strips, and tri strips.
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*/
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*/
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if (sctx->b.screen->info.max_se < 4 ||
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if (sscreen->b.info.max_se < 4 ||
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prim == PIPE_PRIM_POLYGON ||
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key->u.prim == PIPE_PRIM_POLYGON ||
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prim == PIPE_PRIM_LINE_LOOP ||
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key->u.prim == PIPE_PRIM_LINE_LOOP ||
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prim == PIPE_PRIM_TRIANGLE_FAN ||
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key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
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prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
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key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
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(info->primitive_restart &&
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(key->u.primitive_restart &&
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(sctx->b.family < CHIP_POLARIS10 ||
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(sscreen->b.family < CHIP_POLARIS10 ||
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(prim != PIPE_PRIM_POINTS &&
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(key->u.prim != PIPE_PRIM_POINTS &&
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prim != PIPE_PRIM_LINE_STRIP &&
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key->u.prim != PIPE_PRIM_LINE_STRIP &&
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prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
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key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
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info->count_from_stream_output)
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key->u.count_from_stream_output)
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wd_switch_on_eop = true;
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wd_switch_on_eop = true;
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/* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
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/* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
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* We don't know that for indirect drawing, so treat it as
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* We don't know that for indirect drawing, so treat it as
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* always problematic. */
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* always problematic. */
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if (sctx->b.family == CHIP_HAWAII &&
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if (sscreen->b.family == CHIP_HAWAII &&
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(info->indirect || info->instance_count > 1))
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key->u.uses_instancing)
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wd_switch_on_eop = true;
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wd_switch_on_eop = true;
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/* Performance recommendation for 4 SE Gfx7-8 parts if
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/* Performance recommendation for 4 SE Gfx7-8 parts if
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@ -353,42 +344,27 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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* Assume indirect draws always use small instances.
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* Assume indirect draws always use small instances.
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* This is needed for good VS wave utilization.
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* This is needed for good VS wave utilization.
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*/
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*/
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if (sctx->b.chip_class <= VI &&
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if (sscreen->b.chip_class <= VI &&
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sctx->b.screen->info.max_se >= 4 &&
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sscreen->b.info.max_se == 4 &&
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(info->indirect ||
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key->u.multi_instances_smaller_than_primgroup)
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(info->instance_count > 1 &&
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si_num_prims_for_vertices(info) < primgroup_size)))
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wd_switch_on_eop = true;
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wd_switch_on_eop = true;
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/* Required on CIK and later. */
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/* Required on CIK and later. */
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if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
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if (sscreen->b.info.max_se > 2 && !wd_switch_on_eop)
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ia_switch_on_eoi = true;
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ia_switch_on_eoi = true;
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/* Required by Hawaii and, for some special cases, by VI. */
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/* Required by Hawaii and, for some special cases, by VI. */
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if (ia_switch_on_eoi &&
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if (ia_switch_on_eoi &&
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(sctx->b.family == CHIP_HAWAII ||
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(sscreen->b.family == CHIP_HAWAII ||
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(sctx->b.chip_class == VI &&
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(sscreen->b.chip_class == VI &&
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(sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
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(key->u.uses_gs || max_primgroup_in_wave != 2))))
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partial_vs_wave = true;
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partial_vs_wave = true;
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/* Instancing bug on Bonaire. */
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/* Instancing bug on Bonaire. */
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if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
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if (sscreen->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
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(info->indirect || info->instance_count > 1))
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key->u.uses_instancing)
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partial_vs_wave = true;
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partial_vs_wave = true;
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/* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
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* The hw doc says all multi-SE chips are affected, but Vulkan
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* only applies it to Hawaii. Do what Vulkan does.
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*/
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if (sctx->b.family == CHIP_HAWAII &&
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sctx->gs_shader.cso &&
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ia_switch_on_eoi &&
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(info->indirect ||
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(info->instance_count > 1 &&
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si_num_prims_for_vertices(info) <= 1)))
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sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
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/* If the WD switch is false, the IA switch must be false too. */
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/* If the WD switch is false, the IA switch must be false too. */
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assert(wd_switch_on_eop || !ia_switch_on_eop);
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assert(wd_switch_on_eop || !ia_switch_on_eop);
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}
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}
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@ -397,20 +373,92 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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if (ia_switch_on_eoi)
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if (ia_switch_on_eoi)
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partial_es_wave = true;
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partial_es_wave = true;
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/* GS requirement. */
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if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
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partial_es_wave = true;
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return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
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return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
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S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
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S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
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S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
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S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
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S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
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S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
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S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
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S_028AA8_WD_SWITCH_ON_EOP(sscreen->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
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S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
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S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->b.chip_class >= VI ?
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S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
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max_primgroup_in_wave : 0);
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max_primgroup_in_wave : 0);
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}
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}
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void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
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{
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for (int prim = 0; prim <= R600_PRIM_RECTANGLE_LIST; prim++)
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for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
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for (int multi_instances = 0; multi_instances < 2; multi_instances++)
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for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
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for (int count_from_so = 0; count_from_so < 2; count_from_so++)
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for (int line_stipple = 0; line_stipple < 2; line_stipple++)
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for (int uses_tess = 0; uses_tess < 2; uses_tess++)
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for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
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for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
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union si_vgt_param_key key;
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key.index = 0;
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key.u.prim = prim;
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key.u.uses_instancing = uses_instancing;
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key.u.multi_instances_smaller_than_primgroup = multi_instances;
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key.u.primitive_restart = primitive_restart;
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key.u.count_from_stream_output = count_from_so;
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key.u.line_stipple_enabled = line_stipple;
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key.u.uses_tess = uses_tess;
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key.u.tcs_tes_uses_prim_id = tess_uses_primid;
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key.u.uses_gs = uses_gs;
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sctx->ia_multi_vgt_param[key.index] =
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si_get_init_multi_vgt_param(sctx->screen, &key);
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}
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}
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static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
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const struct pipe_draw_info *info,
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unsigned num_patches)
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{
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union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
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|
unsigned primgroup_size;
|
||||||
|
unsigned ia_multi_vgt_param;
|
||||||
|
|
||||||
|
if (sctx->tes_shader.cso) {
|
||||||
|
primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
|
||||||
|
} else if (sctx->gs_shader.cso) {
|
||||||
|
primgroup_size = 64; /* recommended with a GS */
|
||||||
|
} else {
|
||||||
|
primgroup_size = 128; /* recommended without a GS and tess */
|
||||||
|
}
|
||||||
|
|
||||||
|
key.u.prim = info->mode;
|
||||||
|
key.u.uses_instancing = info->indirect || info->instance_count > 1;
|
||||||
|
key.u.multi_instances_smaller_than_primgroup =
|
||||||
|
info->indirect ||
|
||||||
|
(info->instance_count > 1 &&
|
||||||
|
si_num_prims_for_vertices(info) < primgroup_size);
|
||||||
|
key.u.primitive_restart = info->primitive_restart;
|
||||||
|
key.u.count_from_stream_output = info->count_from_stream_output != NULL;
|
||||||
|
|
||||||
|
ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
|
||||||
|
S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
|
||||||
|
|
||||||
|
if (sctx->gs_shader.cso) {
|
||||||
|
/* GS requirement. */
|
||||||
|
if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
|
||||||
|
ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
|
||||||
|
|
||||||
|
/* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
|
||||||
|
* The hw doc says all multi-SE chips are affected, but Vulkan
|
||||||
|
* only applies it to Hawaii. Do what Vulkan does.
|
||||||
|
*/
|
||||||
|
if (sctx->b.family == CHIP_HAWAII &&
|
||||||
|
G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
|
||||||
|
(info->indirect ||
|
||||||
|
(info->instance_count > 1 &&
|
||||||
|
si_num_prims_for_vertices(info) <= 1)))
|
||||||
|
sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ia_multi_vgt_param;
|
||||||
|
}
|
||||||
|
|
||||||
static void si_emit_scratch_reloc(struct si_context *sctx)
|
static void si_emit_scratch_reloc(struct si_context *sctx)
|
||||||
{
|
{
|
||||||
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
|
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
|
||||||
|
|
|
@ -1720,6 +1720,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
|
||||||
|
|
||||||
sctx->gs_shader.cso = sel;
|
sctx->gs_shader.cso = sel;
|
||||||
sctx->gs_shader.current = sel ? sel->first_variant : NULL;
|
sctx->gs_shader.current = sel ? sel->first_variant : NULL;
|
||||||
|
sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
|
||||||
sctx->do_update_shaders = true;
|
sctx->do_update_shaders = true;
|
||||||
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
||||||
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
|
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
|
||||||
|
@ -1729,6 +1730,15 @@ static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
|
||||||
r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
|
r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
|
||||||
|
{
|
||||||
|
sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
|
||||||
|
(sctx->tes_shader.cso &&
|
||||||
|
sctx->tes_shader.cso->info.uses_primid) ||
|
||||||
|
(sctx->tcs_shader.cso &&
|
||||||
|
sctx->tcs_shader.cso->info.uses_primid);
|
||||||
|
}
|
||||||
|
|
||||||
static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
|
static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
|
||||||
{
|
{
|
||||||
struct si_context *sctx = (struct si_context *)ctx;
|
struct si_context *sctx = (struct si_context *)ctx;
|
||||||
|
@ -1740,6 +1750,7 @@ static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
|
||||||
|
|
||||||
sctx->tcs_shader.cso = sel;
|
sctx->tcs_shader.cso = sel;
|
||||||
sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
|
sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
|
||||||
|
si_update_tcs_tes_uses_prim_id(sctx);
|
||||||
sctx->do_update_shaders = true;
|
sctx->do_update_shaders = true;
|
||||||
|
|
||||||
if (enable_changed)
|
if (enable_changed)
|
||||||
|
@ -1757,6 +1768,8 @@ static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
|
||||||
|
|
||||||
sctx->tes_shader.cso = sel;
|
sctx->tes_shader.cso = sel;
|
||||||
sctx->tes_shader.current = sel ? sel->first_variant : NULL;
|
sctx->tes_shader.current = sel ? sel->first_variant : NULL;
|
||||||
|
sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
|
||||||
|
si_update_tcs_tes_uses_prim_id(sctx);
|
||||||
sctx->do_update_shaders = true;
|
sctx->do_update_shaders = true;
|
||||||
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
si_mark_atom_dirty(sctx, &sctx->clip_regs);
|
||||||
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
|
sctx->last_rast_prim = -1; /* reset this so that it gets updated */
|
||||||
|
|
Loading…
Reference in New Issue