pan/mdg: eliminate references to ins->alu.reg_mode
In an effort to simplify MIR by not prepacking instructions, this commit removes references to `ins->alu.reg_mode` so that we can later remove the `ins->alu` field from midgard_instruction. Every place that was using reg_mode was changed to now use the generic `ins->src_type` field instead. We then reconstruct the reg_mode field right before emission. Signed-off-by: Italo Nicola <italonicola@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5933>
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@ -523,6 +523,8 @@ uint16_t mir_round_bytemask_up(uint16_t mask, unsigned bits);
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void mir_set_bytemask(midgard_instruction *ins, uint16_t bytemask);
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signed mir_upper_override(midgard_instruction *ins, unsigned inst_size);
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unsigned mir_components_for_type(nir_alu_type T);
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unsigned max_bitsize_for_alu(midgard_instruction *ins);
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midgard_reg_mode reg_mode_for_bitsize(unsigned bitsize);
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/* MIR printing */
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@ -555,7 +557,6 @@ v_mov(unsigned src, unsigned dest)
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.dest_type = nir_type_uint32,
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.op = midgard_alu_op_imov,
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.alu = {
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.reg_mode = midgard_reg_mode_32,
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.outmod = midgard_outmod_int_wrap
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},
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};
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@ -706,60 +706,6 @@ nir_is_non_scalar_swizzle(nir_alu_src *src, unsigned nr_components)
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op = midgard_alu_op_##_op; \
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ALU_CHECK_CMP(sext); \
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break;
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/* Analyze the sizes of the dest and inputs to determine reg mode. */
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static midgard_reg_mode
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reg_mode_for_nir(nir_alu_instr *instr)
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{
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unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
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unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
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unsigned max_bitsize = MAX2(src_bitsize, dst_bitsize);
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/* We don't have fp16 LUTs, so we'll want to emit code like:
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*
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* vlut.fsinr hr0, hr0
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*
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* where both input and output are 16-bit but the operation is carried
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* out in 32-bit
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*/
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switch (instr->op) {
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case nir_op_fsqrt:
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case nir_op_frcp:
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case nir_op_frsq:
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case nir_op_fsin:
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case nir_op_fcos:
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case nir_op_fexp2:
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case nir_op_flog2:
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max_bitsize = MAX2(max_bitsize, 32);
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break;
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/* These get lowered to moves */
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case nir_op_pack_32_4x8:
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max_bitsize = 8;
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break;
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case nir_op_pack_32_2x16:
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max_bitsize = 16;
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break;
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default:
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break;
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}
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switch (max_bitsize) {
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/* Use 16 pipe for 8 since we don't support vec16 yet */
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case 8:
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case 16:
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return midgard_reg_mode_16;
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case 32:
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return midgard_reg_mode_32;
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case 64:
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return midgard_reg_mode_64;
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default:
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unreachable("Invalid bit size");
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}
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}
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/* Compare mir_lower_invert */
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static bool
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@ -912,10 +858,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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unsigned broadcast_swizzle = 0;
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/* What register mode should we operate in? */
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midgard_reg_mode reg_mode =
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reg_mode_for_nir(instr);
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/* Should we swap arguments? */
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bool flip_src12 = false;
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@ -1220,7 +1162,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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ins.mask = mask_of(nr_components);
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midgard_vector_alu alu = {
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.reg_mode = reg_mode,
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.outmod = outmod,
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};
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@ -2443,6 +2384,61 @@ inline_alu_constants(compiler_context *ctx, midgard_block *block)
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}
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}
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unsigned
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max_bitsize_for_alu(midgard_instruction *ins)
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{
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unsigned max_bitsize = 0;
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for (int i = 0; i < MIR_SRC_COUNT; i++) {
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if (ins->src[i] == ~0) continue;
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unsigned src_bitsize = nir_alu_type_get_type_size(ins->src_types[i]);
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max_bitsize = MAX2(src_bitsize, max_bitsize);
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}
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unsigned dst_bitsize = nir_alu_type_get_type_size(ins->dest_type);
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max_bitsize = MAX2(dst_bitsize, max_bitsize);
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/* We don't have fp16 LUTs, so we'll want to emit code like:
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*
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* vlut.fsinr hr0, hr0
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*
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* where both input and output are 16-bit but the operation is carried
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* out in 32-bit
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*/
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switch (ins->op) {
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case midgard_alu_op_fsqrt:
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case midgard_alu_op_frcp:
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case midgard_alu_op_frsqrt:
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case midgard_alu_op_fsin:
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case midgard_alu_op_fcos:
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case midgard_alu_op_fexp2:
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case midgard_alu_op_flog2:
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max_bitsize = MAX2(max_bitsize, 32);
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break;
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default:
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break;
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}
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return max_bitsize;
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}
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midgard_reg_mode
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reg_mode_for_bitsize(unsigned bitsize)
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{
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switch (bitsize) {
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/* use 16 pipe for 8 since we don't support vec16 yet */
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case 8:
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case 16:
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return midgard_reg_mode_16;
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case 32:
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return midgard_reg_mode_32;
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case 64:
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return midgard_reg_mode_64;
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default:
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unreachable("invalid bit size");
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}
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}
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/* Midgard supports two types of constants, embedded constants (128-bit) and
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* inline constants (16-bit). Sometimes, especially with scalar ops, embedded
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* constants can be demoted to inline constants, for space savings and
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@ -2458,9 +2454,11 @@ embedded_to_inline_constant(compiler_context *ctx, midgard_block *block)
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/* Blend constants must not be inlined by definition */
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if (ins->has_blend_constant) continue;
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unsigned max_bitsize = max_bitsize_for_alu(ins);
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/* We can inline 32-bit (sometimes) or 16-bit (usually) */
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bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
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bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
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bool is_16 = max_bitsize == 16;
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bool is_32 = max_bitsize == 32;
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if (!(is_16 || is_32))
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continue;
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@ -47,7 +47,7 @@ static unsigned
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mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar)
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{
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bool integer = midgard_is_integer_op(ins->op);
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unsigned base_size = (8 << ins->alu.reg_mode);
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unsigned base_size = max_bitsize_for_alu(ins);
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unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]);
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bool half = (sz == (base_size >> 1));
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@ -172,7 +172,7 @@ mir_pack_mask_alu(midgard_instruction *ins)
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* override to the lower or upper half, shifting the effective mask in
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* the latter, so AAAA.... becomes AAAA */
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unsigned inst_size = 8 << ins->alu.reg_mode;
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unsigned inst_size = max_bitsize_for_alu(ins);
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signed upper_shift = mir_upper_override(ins, inst_size);
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if (upper_shift >= 0) {
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@ -184,9 +184,9 @@ mir_pack_mask_alu(midgard_instruction *ins)
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ins->alu.dest_override = midgard_dest_override_none;
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}
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if (ins->alu.reg_mode == midgard_reg_mode_32)
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if (inst_size == 32)
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ins->alu.mask = expand_writemask(effective, 2);
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else if (ins->alu.reg_mode == midgard_reg_mode_64)
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else if (inst_size == 64)
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ins->alu.mask = expand_writemask(effective, 1);
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else
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ins->alu.mask = effective;
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@ -280,8 +280,7 @@ mir_pack_vector_srcs(midgard_instruction *ins)
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{
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bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props);
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midgard_reg_mode mode = ins->alu.reg_mode;
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unsigned base_size = (8 << mode);
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unsigned base_size = max_bitsize_for_alu(ins);
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for (unsigned i = 0; i < 2; ++i) {
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if (ins->has_inline_constant && (i == 1))
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@ -297,7 +296,7 @@ mir_pack_vector_srcs(midgard_instruction *ins)
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assert((sz == base_size) || half);
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unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
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ins->src_types[i], ins->alu.reg_mode,
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ins->src_types[i], reg_mode_for_bitsize(base_size),
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channeled, &rep_lo, &rep_hi);
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midgard_vector_alu_src pack = {
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@ -488,6 +487,15 @@ mir_lower_roundmode(midgard_instruction *ins)
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}
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}
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static midgard_vector_alu
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vector_alu_from_instr(midgard_instruction *ins)
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{
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midgard_vector_alu alu = ins->alu;
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alu.op = ins->op;
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alu.reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
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return alu;
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}
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static void
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emit_alu_bundle(compiler_context *ctx,
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midgard_bundle *bundle,
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@ -532,8 +540,7 @@ emit_alu_bundle(compiler_context *ctx,
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mir_pack_mask_alu(ins);
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mir_pack_vector_srcs(ins);
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size = sizeof(midgard_vector_alu);
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source_alu = ins->alu;
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source_alu.op = ins->op;
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source_alu = vector_alu_from_instr(ins);
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source = &source_alu;
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} else if (ins->unit == ALU_ENAB_BR_COMPACT) {
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size = sizeof(midgard_branch_cond);
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@ -543,8 +550,7 @@ emit_alu_bundle(compiler_context *ctx,
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source = &ins->branch_extended;
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} else {
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size = sizeof(midgard_scalar_alu);
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source_alu = ins->alu;
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source_alu.op = ins->op;
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source_alu = vector_alu_from_instr(ins);
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scalarized = vector_to_scalar_alu(source_alu, ins);
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source = &scalarized;
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}
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@ -244,6 +244,7 @@ mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
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src = vector_alu_from_unsigned(ins->alu.src2);
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unsigned *swizzle = ins->swizzle[src_idx];
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midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins));
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unsigned comp_mask = effective_writemask(ins->op, ins->mask);
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unsigned num_comp = util_bitcount(comp_mask);
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unsigned max_comp = mir_components_for_type(ins->dest_type);
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@ -264,7 +265,7 @@ mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
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printf(", ");
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mir_print_constant_component(stdout, &ins->constants,
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swizzle[comp], ins->alu.reg_mode,
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swizzle[comp], reg_mode,
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src.half, src.mod, ins->op);
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}
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@ -197,9 +197,6 @@ midgard_promote_uniforms(compiler_context *ctx)
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mov.dest_type = nir_type_uint | type_size;
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mov.src_types[0] = mov.dest_type;
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if (type_size == 64)
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mov.alu.reg_mode = midgard_reg_mode_64;
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uint16_t rounded = mir_round_bytemask_up(mir_bytemask(ins), type_size);
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mir_set_bytemask(&mov, rounded);
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mir_insert_instruction_before(ctx, ins, mov);
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