radeonsi: make texture_discard_cmask/eliminate functions non-static
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81dd4a7637
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@ -599,6 +599,10 @@ void si_texture_get_fmask_info(struct si_screen *sscreen,
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void si_texture_get_cmask_info(struct si_screen *sscreen,
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struct r600_texture *rtex,
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struct r600_cmask_info *out);
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void si_eliminate_fast_color_clear(struct r600_common_context *rctx,
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struct r600_texture *rtex);
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void si_texture_discard_cmask(struct si_screen *sscreen,
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struct r600_texture *rtex);
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bool si_init_flushed_depth_texture(struct pipe_context *ctx,
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struct pipe_resource *texture,
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struct r600_texture **staging);
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@ -36,8 +36,6 @@
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#include "state_tracker/drm_driver.h"
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#include "amd/common/sid.h"
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static void r600_texture_discard_cmask(struct si_screen *sscreen,
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struct r600_texture *rtex);
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static enum radeon_surf_mode
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r600_choose_tiling(struct si_screen *sscreen,
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const struct pipe_resource *templ);
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@ -90,7 +88,7 @@ bool si_prepare_for_dma_blit(struct r600_common_context *rctx,
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src_box->height, src_box->depth))
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return false;
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r600_texture_discard_cmask(rctx->screen, rdst);
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si_texture_discard_cmask(rctx->screen, rdst);
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}
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/* All requirements are met. Prepare textures for SDMA. */
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@ -382,7 +380,7 @@ static void r600_surface_import_metadata(struct si_screen *sscreen,
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}
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}
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static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
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void si_eliminate_fast_color_clear(struct r600_common_context *rctx,
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struct r600_texture *rtex)
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{
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struct si_screen *sscreen = rctx->screen;
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@ -398,7 +396,7 @@ static void r600_eliminate_fast_color_clear(struct r600_common_context *rctx,
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mtx_unlock(&sscreen->aux_context_lock);
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}
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static void r600_texture_discard_cmask(struct si_screen *sscreen,
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void si_texture_discard_cmask(struct si_screen *sscreen,
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struct r600_texture *rtex)
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{
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if (!rtex->cmask.size)
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@ -531,7 +529,7 @@ static void r600_reallocate_texture_inplace(struct r600_common_context *rctx,
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}
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if (new_bind_flag == PIPE_BIND_LINEAR) {
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r600_texture_discard_cmask(rctx->screen, rtex);
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si_texture_discard_cmask(rctx->screen, rtex);
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r600_texture_discard_dcc(rctx->screen, rtex);
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}
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@ -725,7 +723,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
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if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
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(rtex->cmask.size || rtex->dcc_offset)) {
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/* Eliminate fast clear (both CMASK and DCC) */
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r600_eliminate_fast_color_clear(rctx, rtex);
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si_eliminate_fast_color_clear(rctx, rtex);
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/* eliminate_fast_color_clear flushes the context */
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flush = false;
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@ -733,7 +731,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
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* to be called.
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*/
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if (rtex->cmask.size)
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r600_texture_discard_cmask(sscreen, rtex);
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si_texture_discard_cmask(sscreen, rtex);
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}
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/* Set metadata. */
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@ -2270,7 +2268,7 @@ void vi_separate_dcc_try_enable(struct r600_common_context *rctx,
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assert(tex->surface.num_dcc_levels);
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assert(!tex->dcc_separate_buffer);
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r600_texture_discard_cmask(rctx->screen, tex);
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si_texture_discard_cmask(rctx->screen, tex);
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/* Get a DCC buffer. */
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if (tex->last_dcc_separate_buffer) {
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