anv/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set. Suggested-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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@ -3640,4 +3640,9 @@
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<field name="Headerless Message for Pre-emptable Contexts Mask" start="21" end="21" type="bool"/>
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</register>
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<register name="HALF_SLICE_CHICKEN7" length="1" num="0x0e194">
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<field name="Enabled Texel Offset Precision Fix" start="1" end="1" type="bool"/>
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<field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/>
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</register>
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</genxml>
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@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device)
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lri.RegisterOffset = GENX(SAMPLER_MODE_num);
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lri.DataDWord = sampler_mode;
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}
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/* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
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* HALF_SLICE_CHICKEN7 register.
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*/
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uint32_t half_slice_chicken7;
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anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
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.EnabledTexelOffsetPrecisionFix = true,
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.EnabledTexelOffsetPrecisionFixMask = true);
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anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
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lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
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lri.DataDWord = half_slice_chicken7;
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}
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#endif
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/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so
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