radeonsi: remove vs.ucps_enabled from the shader key
Written CLIPDIST outputs are simply disabled in PA_CL_VS_OUT_CNTL. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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@ -870,9 +870,6 @@ static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
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for (reg_index = 0; reg_index < 2; reg_index ++) {
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LLVMValueRef *args = pos[2 + reg_index];
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if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
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continue;
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shader->clip_dist_write |= 0xf << (4 * reg_index);
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args[5] =
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@ -1175,9 +1172,6 @@ handle_semantic:
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param_count++;
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break;
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case TGSI_SEMANTIC_CLIPDIST:
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if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
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(1 << semantic_index)))
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continue;
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shader->clip_dist_write |=
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0xf << (semantic_index * 4);
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target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
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@ -145,7 +145,6 @@ union si_shader_key {
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/* The mask of "get_unique_index" bits, needed for ES,
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* it describes how the ES->GS ring buffer is laid out. */
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uint64_t gs_used_inputs;
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unsigned ucps_enabled:2;
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unsigned as_es:1;
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} vs;
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};
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@ -2193,14 +2193,6 @@ static INLINE void si_shader_selector_key(struct pipe_context *ctx,
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struct si_context *sctx = (struct si_context *)ctx;
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memset(key, 0, sizeof(*key));
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if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) &&
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sctx->queued.named.rasterizer) {
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if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
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key->vs.ucps_enabled |= 0x2;
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if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf)
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key->vs.ucps_enabled |= 0x1;
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}
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if (sel->type == PIPE_SHADER_VERTEX) {
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unsigned i;
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if (!sctx->vertex_elements)
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