aco: Emit fewer branches for NGG VS/TES with late primitive export.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10106>
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@ -10325,33 +10325,6 @@ static void export_vs_psiz_layer_viewport_vrs(isel_context *ctx, int *next_pos)
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ctx->block->instructions.emplace_back(std::move(exp));
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}
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static void create_export_phis(isel_context *ctx)
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{
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/* Used when exports are needed, but the output temps are defined in a preceding block.
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* This function will set up phis in order to access the outputs in the next block.
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*/
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assert(ctx->block->instructions.back()->opcode == aco_opcode::p_logical_start);
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aco_ptr<Instruction> logical_start = aco_ptr<Instruction>(ctx->block->instructions.back().release());
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ctx->block->instructions.pop_back();
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Builder bld(ctx->program, ctx->block);
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for (unsigned slot = 0; slot <= VARYING_SLOT_VAR31; ++slot) {
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uint64_t mask = ctx->outputs.mask[slot];
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for (unsigned i = 0; i < 4; ++i) {
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if (!(mask & (1 << i)))
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continue;
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Temp old = ctx->outputs.temps[slot * 4 + i];
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Temp phi = bld.pseudo(aco_opcode::p_phi, bld.def(v1), old, Operand(v1));
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ctx->outputs.temps[slot * 4 + i] = phi;
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}
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}
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bld.insert(std::move(logical_start));
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}
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static void create_vs_exports(isel_context *ctx)
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{
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assert(ctx->stage.hw == HWStage::VS || ctx->stage.hw == HWStage::NGG);
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@ -11300,9 +11273,7 @@ void ngg_nogs_export_primitives(isel_context *ctx)
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void ngg_nogs_export_prim_id(isel_context *ctx)
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{
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if (!ctx->args->options->key.vs_common_out.export_prim_id)
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return;
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assert(ctx->args->options->key.vs_common_out.export_prim_id);
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Temp prim_id;
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if (ctx->stage == vertex_ngg) {
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@ -11329,17 +11300,6 @@ void ngg_nogs_export_prim_id(isel_context *ctx)
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export_vs_varying(ctx, VARYING_SLOT_PRIMITIVE_ID, false, nullptr);
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}
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void ngg_nogs_export_vertices(isel_context *ctx)
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{
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Builder bld(ctx->program, ctx->block);
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/* Export VS outputs */
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create_vs_exports(ctx);
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/* Export primitive ID */
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ngg_nogs_export_prim_id(ctx);
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}
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void ngg_nogs_prelude(isel_context *ctx)
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{
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ngg_emit_sendmsg_gs_alloc_req(ctx);
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@ -11352,19 +11312,19 @@ void ngg_nogs_late_export_finale(isel_context *ctx)
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{
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assert(!ctx->ngg_nogs_early_prim_export);
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/* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
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create_export_phis(ctx);
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/* Export VS/TES primitives. */
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ngg_nogs_export_primitives(ctx);
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/* What comes next must be executed on ES threads. */
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/* Export the primitive ID for VS - needs to read LDS written by GS threads. */
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if (ctx->args->options->key.vs_common_out.export_prim_id && ctx->stage.has(SWStage::VS)) {
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if_context ic;
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Temp is_es_thread = merged_wave_info_to_mask(ctx, 0);
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begin_divergent_if_then(ctx, &ic, is_es_thread);
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ngg_nogs_export_vertices(ctx);
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ngg_nogs_export_prim_id(ctx);
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begin_divergent_if_else(ctx, &ic);
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end_divergent_if(ctx, &ic);
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}
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}
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std::pair<Temp, Temp> ngg_gs_workgroup_reduce_and_scan(isel_context *ctx, Temp src_mask)
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{
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@ -11853,8 +11813,10 @@ void select_program(Program *program,
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if (ctx.stage.hw == HWStage::VS) {
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create_vs_exports(&ctx);
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} else if (ngg_no_gs && ctx.ngg_nogs_early_prim_export) {
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ngg_nogs_export_vertices(&ctx);
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} else if (ngg_no_gs) {
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create_vs_exports(&ctx);
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if (ctx.args->options->key.vs_common_out.export_prim_id && (ctx.ngg_nogs_early_prim_export || ctx.stage.has(SWStage::TES)))
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ngg_nogs_export_prim_id(&ctx);
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} else if (nir->info.stage == MESA_SHADER_GEOMETRY && !ngg_gs) {
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Builder bld(ctx.program, ctx.block);
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bld.barrier(aco_opcode::p_barrier,
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