diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 7e19b89e030..5098970e6f8 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -803,6 +803,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
                   clear_value = si_get_htile_clear_value(zstex, depth);
                   *buffers &= ~PIPE_CLEAR_DEPTH;
                   zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+                  zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
                   update_db_depth_clear = true;
                }
             } else if ((*buffers & PIPE_BIND_DEPTH_STENCIL) == PIPE_BIND_DEPTH_STENCIL) {
@@ -812,6 +813,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
                   clear_value = si_get_htile_clear_value(zstex, depth);
                   *buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
                   zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+                  zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
                   zstex->stencil_cleared_level_mask |= BITFIELD_BIT(level);
                   update_db_depth_clear = true;
                   update_db_stencil_clear = true;
@@ -876,6 +878,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
                clear_types |= SI_CLEAR_TYPE_HTILE;
                *buffers &= ~PIPE_CLEAR_DEPTH;
                zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+               zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
                update_db_depth_clear = true;
             }
          } else if ((*buffers & PIPE_BIND_DEPTH_STENCIL) == PIPE_BIND_DEPTH_STENCIL) {
@@ -889,6 +892,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
                clear_types |= SI_CLEAR_TYPE_HTILE;
                *buffers &= ~PIPE_CLEAR_DEPTHSTENCIL;
                zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+               zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
                zstex->stencil_cleared_level_mask |= BITFIELD_BIT(level);
                update_db_depth_clear = true;
                update_db_stencil_clear = true;
@@ -914,6 +918,7 @@ static void si_fast_clear(struct si_context *sctx, unsigned *buffers,
                clear_types |= SI_CLEAR_TYPE_HTILE;
                *buffers &= ~PIPE_CLEAR_DEPTH;
                zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(level);
+               zstex->depth_cleared_level_mask |= BITFIELD_BIT(level);
                update_db_depth_clear = true;
             } else if (htile_size &&
                        !(*buffers & PIPE_CLEAR_DEPTH) &&
@@ -971,9 +976,6 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
    else if (!util_format_has_stencil(util_format_description(zsbuf->format)))
       buffers &= ~PIPE_CLEAR_STENCIL;
 
-   if (buffers & PIPE_CLEAR_DEPTH)
-      zstex->depth_cleared_level_mask |= BITFIELD_BIT(zsbuf->u.tex.level);
-
    si_fast_clear(sctx, &buffers, color, depth, stencil);
    if (!buffers)
       return; /* all buffers have been cleared */
@@ -1056,6 +1058,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
       sctx->db_depth_clear = false;
       sctx->db_depth_disable_expclear = false;
       zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(zsbuf->u.tex.level);
+      zstex->depth_cleared_level_mask |= BITFIELD_BIT(zsbuf->u.tex.level);
       si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
    }
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 672c7e1d321..611bb22afcf 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -387,7 +387,7 @@ struct si_texture {
    float depth_clear_value[RADEON_SURF_MAX_LEVELS];
    uint8_t stencil_clear_value[RADEON_SURF_MAX_LEVELS];
    uint16_t depth_cleared_level_mask_once; /* if it was cleared at least once */
-   uint16_t depth_cleared_level_mask;     /* track if it was cleared (not 100% accurate) */
+   uint16_t depth_cleared_level_mask;     /* track if it's cleared (can be false negative) */
    uint16_t stencil_cleared_level_mask; /* if it was cleared at least once */
    uint16_t dirty_level_mask;         /* each bit says if that mipmap is compressed */
    uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.cpp b/src/gallium/drivers/radeonsi/si_state_draw.cpp
index ecaa6cec016..e806d8a89ae 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_draw.cpp
@@ -2463,7 +2463,7 @@ static void si_draw(struct pipe_context *ctx,
          sctx->num_prim_restart_calls += num_draws;
    }
 
-   if (!sctx->blitter_running && sctx->framebuffer.state.zsbuf) {
+   if (sctx->framebuffer.state.zsbuf) {
       struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
       zstex->depth_cleared_level_mask &= ~BITFIELD_BIT(sctx->framebuffer.state.zsbuf->u.tex.level);
    }