i965/state: Add a helper for emitting a surface state using isl
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Reviewed-by: Chad Versace <chad.versace@intel.com>
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@ -274,6 +274,13 @@ GLuint translate_tex_format(struct brw_context *brw,
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int brw_get_texture_swizzle(const struct gl_context *ctx,
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const struct gl_texture_object *t);
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void brw_emit_surface_state(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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const struct isl_view *view,
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uint32_t mocs, bool for_gather,
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uint32_t *surf_offset, int surf_index,
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unsigned read_domains, unsigned write_domains);
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void brw_update_renderbuffer_surfaces(struct brw_context *brw,
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const struct gl_framebuffer *fb,
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uint32_t render_target_start,
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@ -35,6 +35,7 @@
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#include "main/mtypes.h"
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#include "main/samplerobj.h"
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#include "main/shaderimage.h"
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#include "main/teximage.h"
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#include "program/prog_parameter.h"
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#include "program/prog_instruction.h"
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#include "main/framebuffer.h"
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@ -52,6 +53,86 @@
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#include "brw_defines.h"
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#include "brw_wm.h"
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struct surface_state_info {
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unsigned num_dwords;
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unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */
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unsigned reloc_dw;
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unsigned aux_reloc_dw;
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unsigned tex_mocs;
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unsigned rb_mocs;
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};
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static const struct surface_state_info surface_state_infos[] = {
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[4] = {6, 32, 1, 0},
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[5] = {6, 32, 1, 0},
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[6] = {6, 32, 1, 0},
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[7] = {8, 32, 1, 6, GEN7_MOCS_L3, GEN7_MOCS_L3},
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[8] = {13, 64, 8, 10, BDW_MOCS_WB, BDW_MOCS_PTE},
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[9] = {16, 64, 8, 10, SKL_MOCS_WB, SKL_MOCS_PTE},
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};
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void
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brw_emit_surface_state(struct brw_context *brw,
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struct intel_mipmap_tree *mt,
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const struct isl_view *view,
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uint32_t mocs, bool for_gather,
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uint32_t *surf_offset, int surf_index,
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unsigned read_domains, unsigned write_domains)
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{
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const struct surface_state_info ss_info = surface_state_infos[brw->gen];
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struct isl_surf surf;
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intel_miptree_get_isl_surf(brw, mt, &surf);
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union isl_color_value clear_color = { .u32 = { 0, 0, 0, 0 } };
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struct isl_surf *aux_surf = NULL, aux_surf_s;
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uint64_t aux_offset = 0;
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enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
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if (mt->mcs_mt &&
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((view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) ||
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mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)) {
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intel_miptree_get_aux_isl_surf(brw, mt, &aux_surf_s, &aux_usage);
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aux_surf = &aux_surf_s;
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assert(mt->mcs_mt->offset == 0);
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aux_offset = mt->mcs_mt->bo->offset64;
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/* We only really need a clear color if we also have an auxiliary
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* surfacae. Without one, it does nothing.
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*/
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clear_color = intel_miptree_get_isl_clear_color(brw, mt);
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}
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uint32_t *dw = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
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ss_info.num_dwords * 4, ss_info.ss_align,
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surf_index, surf_offset);
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isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = view,
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.address = mt->bo->offset64 + mt->offset,
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.aux_surf = aux_surf, .aux_usage = aux_usage,
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.aux_address = aux_offset,
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.mocs = mocs, .clear_color = clear_color);
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drm_intel_bo_emit_reloc(brw->batch.bo,
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*surf_offset + 4 * ss_info.reloc_dw,
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mt->bo, mt->offset,
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read_domains, write_domains);
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if (aux_surf) {
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/* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
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* upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
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* contain other control information. Since buffer addresses are always
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* on 4k boundaries (and thus have their lower 12 bits zero), we can use
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* an ordinary reloc to do the necessary address translation.
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*/
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assert((aux_offset & 0xfff) == 0);
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drm_intel_bo_emit_reloc(brw->batch.bo,
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*surf_offset + 4 * ss_info.aux_reloc_dw,
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mt->mcs_mt->bo, dw[ss_info.aux_reloc_dw] & 0xfff,
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read_domains, write_domains);
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}
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}
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GLuint
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translate_tex_target(GLenum target)
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{
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