gallivm: add support for TGSI instructions with two outputs
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
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@ -264,11 +264,17 @@ lp_build_tgsi_inst_llvm(
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memset(&emit_data, 0, sizeof(emit_data));
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assert(info->num_dst <= 1);
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assert(info->num_dst <= 2);
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if (info->num_dst) {
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TGSI_FOR_EACH_DST0_ENABLED_CHANNEL( inst, chan_index ) {
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emit_data.output[chan_index] = bld_base->base.undef;
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}
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if (info->num_dst >= 2) {
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TGSI_FOR_EACH_DST1_ENABLED_CHANNEL( inst, chan_index ) {
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emit_data.output1[chan_index] = bld_base->base.undef;
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}
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}
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}
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emit_data.inst = inst;
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@ -309,11 +315,21 @@ lp_build_tgsi_inst_llvm(
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TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
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emit_data.output[chan_index] = val;
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}
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if (info->num_dst >= 2) {
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val = emit_data.output1[0];
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memset(emit_data.output1, 0, sizeof(emit_data.output1));
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TGSI_FOR_EACH_DST1_ENABLED_CHANNEL(inst, chan_index) {
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emit_data.output1[chan_index] = val;
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}
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}
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}
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}
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if (info->num_dst > 0 && info->opcode != TGSI_OPCODE_STORE) {
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bld_base->emit_store(bld_base, inst, info, 0, emit_data.output);
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if (info->num_dst >= 2)
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bld_base->emit_store(bld_base, inst, info, 1, emit_data.output1);
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}
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return TRUE;
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}
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@ -81,6 +81,11 @@ struct lp_build_emit_data {
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*/
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LLVMValueRef output[4];
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/**
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* Secondary output for instruction that have a second destination register.
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*/
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LLVMValueRef output1[4];
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/**
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* The current instruction that is being 'executed'.
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*/
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@ -58,6 +58,15 @@ extern "C" {
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TGSI_FOR_EACH_CHANNEL( CHAN )\
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TGSI_IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )
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#define TGSI_IS_DST1_CHANNEL_ENABLED( INST, CHAN )\
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((INST)->Dst[1].Register.WriteMask & (1 << (CHAN)))
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#define TGSI_IF_IS_DST1_CHANNEL_ENABLED( INST, CHAN )\
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if (TGSI_IS_DST1_CHANNEL_ENABLED( INST, CHAN ))
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#define TGSI_FOR_EACH_DST1_ENABLED_CHANNEL( INST, CHAN )\
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TGSI_FOR_EACH_CHANNEL( CHAN )\
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TGSI_IF_IS_DST1_CHANNEL_ENABLED( INST, CHAN )
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/**
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* Registers may be treated as float, signed int or unsigned int.
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