intel/blorp: Define the clear value bounds for HiZ clears
Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:
./bin/depthstencil-render-miplevels 146 d=z32f_s8
Jason found this to fix incorrect clearing on SKL.
Fixes: 09948151ab
("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Jason Ekstrand <jason@jlekstrand.net>
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@ -1628,6 +1628,20 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
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*/
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blorp_emit_3dstate_multisample(batch, params);
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/* From the BDW PRM Volume 7, Depth Buffer Clear:
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*
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* The clear value must be between the min and max depth values
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* (inclusive) defined in the CC_VIEWPORT. If the depth buffer format is
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* D32_FLOAT, then +/-DENORM values are also allowed.
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*
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* Set the bounds to match our hardware limits, [0.0, 1.0].
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*/
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if (params->depth.enabled && params->hiz_op == ISL_AUX_OP_FAST_CLEAR) {
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assert(params->depth.clear_color.f32[0] >= 0.0f);
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assert(params->depth.clear_color.f32[0] <= 1.0f);
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blorp_emit_cc_viewport(batch);
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}
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/* If we can't alter the depth stencil config and multiple layers are
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* involved, the HiZ op will fail. This is because the op requires that a
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* new config is emitted for each additional layer.
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