radeonsi: simplify DCC handling in si_initialize_color_surface
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@ -1926,8 +1926,9 @@ static void si_initialize_color_surface(struct si_context *sctx,
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surf->cb_color_info = color_info;
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surf->cb_color_info = color_info;
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surf->cb_color_attrib = color_attrib;
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surf->cb_color_attrib = color_attrib;
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if (sctx->b.chip_class >= VI) {
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if (sctx->b.chip_class >= VI && rtex->surface.dcc_enabled) {
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unsigned max_uncompressed_block_size = 2;
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unsigned max_uncompressed_block_size = 2;
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uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
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if (rtex->surface.nsamples > 1) {
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if (rtex->surface.nsamples > 1) {
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if (rtex->surface.bpe == 1)
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if (rtex->surface.bpe == 1)
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@ -1938,13 +1939,8 @@ static void si_initialize_color_surface(struct si_context *sctx,
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surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
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surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
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S_028C78_INDEPENDENT_64B_BLOCKS(1);
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S_028C78_INDEPENDENT_64B_BLOCKS(1);
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if (rtex->surface.dcc_enabled) {
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uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
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surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
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surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
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}
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}
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}
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if (rtex->fmask.size) {
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if (rtex->fmask.size) {
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surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
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surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
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